Fast OFDD based minimization of fixed polarity Reed-Muller expressions

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Fast OFDD based minimization of fixed polarity Reed-Muller expressions

Full text

Pdf (582 KB)

Source

European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Grenoble, France

Pages: 2 - 7

Year of Publication: 1994

ISBN:0-89791-685-9

Authors

Rolf Drechsler	Computer Science Department, Johann Wolfgang Goethe-University, D-60054 Frankfurt am Main, Germany
Bernd Becker	Computer Science Department, Johann Wolfgang Goethe-University, D-60054 Frankfurt am Main, Germany
Michael Theobald	Computer Science Department, Johann Wolfgang Goethe-University, D-60054 Frankfurt am Main, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 12

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B. Becker and R. Drechsler. On the computational power of functional decision diagrams. SO. Workrhop iiber Komplezithtstheorie, Datenrtruktunn und efiziente Algorithmen, Berlin, 1993.
	2	B. Becker and R. Drechsler. Testability of circuits do rived from functional decision diagrams. In European Conf. on Design Automation, page 667, 1994.
	3	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	4	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	5	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	6	O. Coudert, H. Fraiese, and J.-C. Madre. A breakthrough in two-level logic minimization. In Int'l Workrhop on Logic Sgnth., page P2b, 1993.
	7	R. Drechsler , A. Sarabi , M. Theobald , B. Becker , M. A. Perkowski, Efficient representation and manipulation of switching functions based on ordered Kronecker functional decision diagrams, Proceedings of the 31st annual conference on Design automation, p.415-419, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196444]
	8	U. Kebschull and W. Rosenstiel. Efficient graph-based computation and manipulation of functional decision diagrams. In European Conf. on Design Automation, pages 278-282, 1993.
	9	U. Kebschull, E. Schubert, and W. Roeenstiel. Multilevel logic synthesis based on functional decision diagrams. In European Conf. on Design Automation, pages 43-47, 1992.
	10	Shin-ichi Minato, Zero-suppressed BDDs for set manipulation in combinatorial problems, Proceedings of the 30th international conference on Design automation, p.272-277, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164890]
	11	M.A. Perkowski and M. Chrzanowska-Jeske. An exact algorithm to minimize mixed-radix exclusive sums of products for incompletely specified boolean functions. In Int'l Sgmp. Circ. and Syrtemr, pages 1652-1655, 1990.
	12	Marek A. Perkowski , Laszlo Csanky , Andisheh Sarabi , Ingo Schäfer, Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.33-36, October 11-14, 1992
	13	S.M. Reddy. Easily testable realizations for logic functions. In IEEE Dunraction on Computers, volume c-21, pages 1183-1188, 1972.
	14	A. Sarabi , M. A. Perkowski, Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks, Proceedings of the 29th ACM/IEEE conference on Design automation, p.30-35, June 08-12, 1992, Anaheim, California, United States
	15	Tsutomu Sasao, Logic Synthesis and Optimization, Kluwer Academic Publishers, Norwell, MA, 1997
	16	T. Sasao , P. Besslich, On the Complexity of Mod-2l Sum PLA's, IEEE Transactions on Computers, v.39 n.2, p.262-266, February 1990 [doi>10.1109/12.45212]
	17	J. Saul. Logic synthesis for arithmetic circuits using the reed-muller representation. In European Conf. on Derign Automation, pages 109-113, 1992.
	18	I. Sch5fer and M.A. Perkowski. Multiple-valued input generalized reed-muUer forms. In Int'l Sgmp. on multi-valued Logic, pages 40-48, 1991.
	19	Detlef Sieling , Ingo Wegener, Reduction of OBDDs in linear time, Information Processing Letters, v.48 n.3, p.139-144, Nov. 19, 1993 [doi>10.1016/0020-0190(93)90256-9]
	20	Chien-Chung Tsai , Malgorzata Marek-Sadowska, Boolean matching using generalized Reed-Muller forms, Proceedings of the 31st annual conference on Design automation, p.339-344, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196404]

CITED BY 12

	E. M. Clarke , M. Fujita , X. Zhao, Hybrid decision diagrams, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.159-163, November 05-09, 1995, San Jose, California, United States
	Yibin Ye , Kaushik Roy, A graph-based synthesis algorithm for AND/XOR networks, Proceedings of the 34th annual conference on Design automation, p.107-112, June 09-13, 1997, Anaheim, California, United States
	Rolf Drechsler, Verifying integrity of decision diagrams, Integration, the VLSI Journal, v.32 n.1-3, p.61-75, November 2002
	Bernd Becker , Rolf Drechsler , Michael Theobald, On the Expressive Power of OKFDDs, Formal Methods in System Design, v.11 n.1, p.5-21, July 1997
	Pejman Lotfi-Kamran , Mohammad Hosseinabady , Hamid Shojaei , Mehran Massoumi , Zainalabedin Navabi, TED+: a data structure for microprocessor verification, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Rolf Drechsler , Bernd Becker , Andrea Jahnke, On Variable Ordering and Decomposition Type Choice in OKFDDs, IEEE Transactions on Computers, v.47 n.12, p.1398-1403, December 1998
	Rolf Drechsler , Harry Hengster , Horst Schäfer , Joachim Hartmann , Bernd Becker, Testability of 2-Level AND/EXOR Circuits, Journal of Electronic Testing: Theory and Applications, v.14 n.3, p.219-225, June 1999
	R. Drechsler , B. Becker, Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions, Proceedings of the 1995 European conference on Design and Test, p.91, March 06-09, 1995
	B. Becker , R. Drechsler, How many decomposition types do we need? [decision diagrams], Proceedings of the 1995 European conference on Design and Test, p.438, March 06-09, 1995
	B. Becker , R. Drechsler, How many decomposition types do we need? [decision diagrams], Proceedings of the 1995 European conference on Design and Test, p.438, March 06-09, 1995
	R. Drechsler , H. Hengster , H. Schafer , J. Hartmann , B. Becker, Testability of 2-level AND/EXOR circuits, Proceedings of the 1997 European conference on Design and Test, p.548, March 17-20, 1997
	Julian F. Miller , Dominic Job , Vesselin K. Vassilev, Principles in the Evolutionary Design of Digital Circuits—Part I, Genetic Programming and Evolvable Machines, v.1 n.1-2, p.7-35, April 2000