Statistical estimation of the switching activity in digital circuits

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Statistical estimation of the switching activity in digital circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 728 - 733

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Michael G. Xakellis	Coordinated Science Lab. & ECE Dept., University of Illinois at Urbana-Champaign, Urbana, Illinois
Farid N. Najm	Coordinated Science Lab. & ECE Dept., University of Illinois at Urbana-Champaign, Urbana, Illinois

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 42, Citation Count: 42

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 310-323, Feb. 1993.
	2	R. Burch, F. Najm, P. "fang, and T. Trick, "A Monte Carlo approach for power estimation," IEEE Transactions on VLSI Systems, vol. 1, no. 1, pp. 63-71, March 1993.
	3	I. Miller and J. Freund, Probability and Statistics for Engineers, 3rd edition. Englewood Cliffs, N J: Prentice-Hall, Inc., 1985.
	4	F. Brglez, P. Pownall, and R. Hum, "Accelerated ATPG and fault grading via testability analysis," IEEE International Symposium on Gircuits and Systems, pp. 695-698, June 1985.
	5	F. Brglez, D. Bryan and K. Kozminski, "Combinational profiles of sequential benchmark circuits," IEEE International Symposium on Gircuits and Systems, pp. 1929-1934, May 1989.

CITED BY 42

	R. Chandramouli , Vamsi K. Srikantam, On mixture density and maximum likelihood power estimation via expectation-maximization, Proceedings of the 2000 conference on Asia South Pacific design automation, p.423-428, January 2000, Yokohama, Japan
	Tan-Li Chou , Kaushik Roy, Statistical estimation of sequential circuit activity, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.34-37, November 05-09, 1995, San Jose, California, United States
	Farid N. Najm, Power estimation techniques for integrated circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.492-499, November 05-09, 1995, San Jose, California, United States
	Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996
	M. Nemani , F. Najm, High-level power estimation and the area complexity of Boolean functions, Proceedings of the 1996 international symposium on Low power electronics and design, p.329-334, August 12-14, 1996, Monterey, California, United States
	Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States
	Alberto Macii , Enrico Macii , Massimo Poncino , Riccardo Scarsi, Stream synthesis for efficient power simulation based on spectral transforms, Proceedings of the 1998 international symposium on Low power electronics and design, p.30-35, August 10-12, 1998, Monterey, California, United States
	Farid N. Najm , Michael Y. Zhang, Extreme delay sensitivity and the worst-case switching activity in VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.623-627, June 12-16, 1995, San Francisco, California, United States
	L. Yuan , C. Teng , S. Kang, Statistical estimation of average power dissipation in CMOS VLSI circuits using nonparametric techniques, Proceedings of the 1996 international symposium on Low power electronics and design, p.73-78, August 12-14, 1996, Monterey, California, United States
	Subodh Gupta , Farid N. Najm, Power macro-models for DSP blocks with application to high-level synthesis, Proceedings of the 1999 international symposium on Low power electronics and design, p.103-105, August 16-17, 1999, San Diego, California, United States
	P. Schneider , S. Krishnamoorthy, Effects of correlations on accuracy of power analysis—an experimental study, Proceedings of the 1996 international symposium on Low power electronics and design, p.113-116, August 12-14, 1996, Monterey, California, United States
	Chuan-Yu Wang , Kaushik Roy, COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.52-55, November 09-13, 1997, San Jose, California, United States
	Yong Je Lim , Kyung-Im Son , Heung-Joon Park , Mani Soma, A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits, Proceedings of the 33rd annual conference on Design automation, p.445-450, June 03-07, 1996, Las Vegas, Nevada, United States
	Anthony M. Hill , Sung-Mo Steve Kang, Determining accuracy bounds for simulation-based switching activity estimation, Proceedings of the 1995 international symposium on Low power design, p.215-220, April 23-26, 1995, Dana Point, California, United States
	Farid N. Najm , Shashank Goel , Ibrahim N. Hajj, Power estimation in sequential circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.635-640, June 12-16, 1995, San Francisco, California, United States
	Lei Wang , Naresh Shanbhag, Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers, Proceedings of the 2001 international symposium on Low power electronics and design, p.334-339, August 2001, Huntington Beach, California, United States
	Subodh Gupta , Farid N. Najm, Energy-per-cycle estimation at RTL, Proceedings of the 1999 international symposium on Low power electronics and design, p.121-126, August 16-17, 1999, San Diego, California, United States
	Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States
	Manish Goel , Naresh R. Shanbhag, Dynamic algorithm transformation (DAT) for low-power adaptive signal processing, Proceedings of the 1997 international symposium on Low power electronics and design, p.161-166, August 18-20, 1997, Monterey, California, United States
	Subodh Gupta , Farid N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual conference on Design automation, p.365-370, June 09-13, 1997, Anaheim, California, United States
	Rajamohana Hegde , Naresh R. Shanbhag, Energy-efficient signal processing via algorithmic noise-tolerance, Proceedings of the 1999 international symposium on Low power electronics and design, p.30-35, August 16-17, 1999, San Diego, California, United States
	Byunggyu Kwak , Eun Sei Park, An optimization-based error calculation for statistical power estimation of CMOS logic circuits, Proceedings of the 35th annual conference on Design automation, p.690-693, June 15-19, 1998, San Francisco, California, United States
	Farid N. Najm, Towards a high-level power estimation capability, Proceedings of the 1995 international symposium on Low power design, p.87-92, April 23-26, 1995, Dana Point, California, United States
	Rajendran Panda , Farid N. Najm, Technology-dependent transformations for low-power synthesis, Proceedings of the 34th annual conference on Design automation, p.650-655, June 09-13, 1997, Anaheim, California, United States
	Victor Kim , Prithviraj Banerjee, Parallel algorithms for power estimation, Proceedings of the 35th annual conference on Design automation, p.672-677, June 15-19, 1998, San Francisco, California, United States
	Rajamohana Hegde , Naresh R. Shanbhag, Soft digital signal processing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.813-823, 12/1/2001
	Vikram Saxena , Farid N. Najm , Ibrahim N. Hajj, Estimation of state line statistics in sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.455-473, July 2002
	Lei Wang , Naresh R. Shanbhag, Low-power MIMO signal processing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.434-445, June 2003
	Subodh Gupta , Farid N. Najm, Energy and peak-current per-cycle estimation at RTL, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.525-537, August 2003
	Ashok K. Murugavel , N. Ranganathan , R. Chandramouli , Srinath Chavali, Least-square estimation of average power in digital CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.55-58, 2/1/2002
	David Ihsin Cheng , Kwang-Ting Cheng , Deborah C. Wang , Malgorzata Marek-Sadowska, A new hybrid methodology for power estimation, Proceedings of the 33rd annual conference on Design automation, p.439-444, June 03-07, 1996, Las Vegas, Nevada, United States
	R. Chandramouli , Vamsi K. Srikantam, Multimode power modeling and maximum-likelihood estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.11, p.1244-1248, November 2004
	Swaroop Appadwedula , Manish Goel , Naresh R. Shanbhag , Douglas L. Jones , Kannan Ramchandran, Total System Energy Minimization for Wireless Image Transmission, Journal of VLSI Signal Processing Systems, v.27 n.1-2, p.99-117, Feb. 2001
	Saeeid Tahmasbi Oskuii , Per Gunnar Kjeldsberg , Einar Johan Aas, Probabilistic gate-level power estimation using a novel waveform set method, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Saeeid Tahmasbi Oskuii , Per Gunnar Kjeldsberg , Oscar Gustafsson, Transition-activity aware design of reduction-stages for parallel multipliers, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Debjit Sinha , DiaaEldin Khalil , Yehea Ismail , Hai Zhou, A timing dependent power estimation framework considering coupling, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Tan-Li Chou , Kaushik Roy, Power Estimation Under Uncertain Delays, Integrated Computer-Aided Engineering, v.5 n.2, p.107-116, April 1998
	Jo Dale Carothers , Radjakichenin Radjassamy, Low Power VLSI Design Techniques - The Current State, Integrated Computer-Aided Engineering, v.5 n.2, p.153-176, April 1998
	S. Manich , J. Figueras, Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model, Proceedings of the 1997 European conference on Design and Test, p.597, March 17-20, 1997
	Vikram Saxena , Farid N. Najm , Ibrahim Hajj, Monte-Carlo Approach for Power Estimation in Sequential Circuits, Proceedings of the 1997 European conference on Design and Test, p.416, March 17-20, 1997
	Hanif Fatemi , Behnam Amelifar , Massoud Pedram, Power optimal MTCMOS repeater insertion for global buses, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Ashoka Sathanur , Antonio Pullini , Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino, Timing-driven row-based power gating, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA