Functional test generation for FSMs by fault extraction

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Functional test generation for FSMs by fault extraction

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 712 - 715

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Bapiraju Vinnakota	Department of Electrical Engineering, University of Minnesota, Minneapolis, MN
Jason Andrews	Tricod Systems Inc., Plymouth, MN and Department of Electrical Engineering, University of Minnesota, Minneapolis, MN

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Peter C. Maxwell , Robert C. Aitken, Test Sets and Reject Rates: All Fault Coverages are Not Created Equal, IEEE Design & Test, v.10 n.1, p.42-51, January 1993 [doi>10.1109/54.199804]
	2	K-T. Cheng and J.Y. Jou, ~A Functional fault model for sequential machines," IEEE T-CAD, pp. 1065-1073, Sep. 1992.
	3	Irith Pomeranz , Sudhakar M. Reddy, On achieving a complete fault coverage for sequential machines using the transition fault model, Proceedings of the 28th conference on ACM/IEEE design automation, p.341-346, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127691]
	4	I. Pomeranz and S.M. Reddy, ~Test generation for synchronous sequential circuits based on fault extraction," in Proc. ICCAD, pp. 450-453, 1991.
	5	M.K. Srinivas, J. Jacob, and V.D. Agrawal, ~Finite state machine testing based on growth and disappearance faults," in Proc. FTCS, 1992, pp. 238-245.
	6	G. Buonanno, F. Fummi, and D. Sciuto, ~Functional fault models and gate level coverage for sequential architectures," in Proc. ICCD., pp. 572-575, Oct. 1993.
	7	M. Abromovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design, Rockville, MD, Computer Science Press, 1990.
	8	H-K.T. Ma, S. Devadas, A.R. Newton and A.S. Vincentelli, ~Test generation for sequential circuits," IEEE T- CAD, pp. 1081-1093, Oct. 1988.
	9	P. Goel, ~An implicit enumeration algorithm to generate tests for combinational logic circuits," IEEE Trans. Comput., pp. 215-222, Mar. 1981.
	10	T.M. Nierman, W.T. Cheng and J.H. Patel, ~PROOFS: A fast memory efficient sequential circuit fault simulator," IEEE T-CAD, pp. 198-207, Feb. 1992.
	11	F. Brglez, D. Bryan, and K. Kozminski, ~Combinational profiles of sequential benchmark circuits," in Proc. IS- CAS., May 1989.
	12	R. Lisanke, ~Finite-state machine benchmark set," Preliminary benchmark collection, Sept. 1987.