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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar, Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.167-175, February 21-23, 1999, Monterey, California, United States
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Michael S. Hsiao , Shuo Sheng , Rajat Arora , Ankur Jain , Vamsi Boppana, Verification of large scale nano systems with unreliable nano devices, Nano, quantum and molecular computing: implications to high level design and validation, Kluwer Academic Publishers, Norwell, MA, 2004
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D. Tadesse , D. Sheffield , E. Lenge , R. I. Bahar , J. Grodstein, Accurate timing analysis using SAT and pattern-dependent delay models, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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