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Dynamic search-space pruning techniques in path sensitization
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents
San Diego, California, United States
Pages: 705 - 711  
Year of Publication: 1994
ISBN:0-89791-653-0
Authors
João P. Marques Silva  Department of Electrical Engineering and Computer Science, University of Michigan
Karem A. Sakallah  Department of Electrical Engineering and Computer Science, University of Michigan
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 12,   Citation Count: 10
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
 
2
F. Brglez, and H. Fujiwara, "A Neutral List of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN," in Proc. Int. Syrup. on Circ. and Sys., 1985.
 
3
R. Dechter, "Learning While Searching in Constraint-Satisfaction Problems," Technical Report CSD-860049, University of California at Los Angeles, June 1986.
 
4
T. Fujino and H. Fujiwara, "An Efficient Test Generation Algorithm Based on Search Space Dominance," in Proc. 22nd Fault Tolerant Cornput. Syrup., pp. 246-253, 1992.
 
5
H. Fujiwara and T. Shimono, "On the Acceleration of Test Generation Algorithms," IEEE Trans. on Computers, vol. 32, no. 12, pp. 1137- 1144, December 1983.
6
 
7
E Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. on Computers, vol. 30, no. 3, pp. 215-222, March 1981.
8
 
9
A. Lioy, "Adaptive Backtrace and Dynamic Partitioning Enhance APTG," in Proc. Int. Conf. Computer Design, pp. 62-65, 1988.
 
10
W. Kunz and D. Pradhan, "Accelerated Dynamic Learning for Test Pattern Generation in Combinational Circuits," IEEE Trans. on Computer- Aided Design, vol. 12, no. 5, pp. 684-694, May 1993.
 
11
S. Mallela and S. Wu, "A Sequential Circuit Test Generation System," in Proc. Int. Test Conf., pp. 57-61, 1985.
 
12
 
13
J. Rajski and H. Cox, "A Method to Calculate Necessary Assignments in Algorithmic Test Pattern Generation," in Proc. Int. Test Conf., pp. 25- 34, 1990.
 
14
J. E Roth, "Diagnosis of Automata Failures: a Calculus and a Method". IBM J. Res. Develop., vol. 10, pp. 278-291, July 1966.
 
15
M. H. Schulz, E. Trischler and T. M. Sarfert, "SOCRATES: A Highly Efficient Automatic Test Pattern Generation System," IEEE Trans. on Computer-Aided Design, vol. 7, no. 1, pp. 126-137, January 1988.
 
16
M. H. Schulz, and E. Auth, "Improved Deterministic Test Pattern Generation with Applications to Redundancy Identification," IEEE Trans. on Computer-AidedDesign, vol. 8, no. 7, pp. 811-816, July 1989.
 
17
J. E M. Silva and K. A. Sakallah, "Search-Space Pruning Heuristics for Path Sensitization in Test Pattern Generation," Technical Report CSE- TR-178-93, University of Michigan, October 1993.
 
18
J. E M. Silva and K. A. Sakallah, "Efficient and Robust Test Generation-Based Timing Analysis," in Proc. Int. Syrup. on Circ. and Sys., 1994, in press.
 
19
R. M. Stallman and G. J. Sussman, "Forward Reasoning and Dependency-Directed Backtracking in a System for Computer-Aided Circuit Analysis," in Artificial Intelligence, 9, pp. 135-196, 1977.
 
20
R. E. Tarjan, "Finding Dominators in Directed Graphs," in SlAM J. Comput., vol. 3, pp. 62-89, 1974.
 
21
J. A. Waicukauski, E A. Shupe, D. J. Giramma and A. Matin, "ATPG for Ultra-Large Structured Designs," in Proc. Int. Test Conf., pp. 44-51, 1990.

CITED BY  10

Collaborative Colleagues:
João P. Marques Silva: colleagues
Karem A. Sakallah: colleagues