Sequential circuit test generation in a genetic algorithm framework

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Sequential circuit test generation in a genetic algorithm framework

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 698 - 704

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Elizabeth M. Rudnick	Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL
Janak H. Patel	Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL
Gary S. Greenstein	Sunrise Test Systems, Inc., Santa Clara, CA
Thomas M. Niermann	Sunrise Test Systems, Inc., Santa Clara, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 34, Citation Count: 33

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 33

	Elizabeth M. Rudnick , Janak H. Patel, Combining deterministic and genetic approaches for sequential circuit test generation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.183-188, June 12-16, 1995, San Francisco, California, United States
	Fulvio Corno , Paolo prinetto , Maurizio Rebaudenpgo , Matteo Sonza Reorda, SAARA: a simulated annealing algorithm for test pattern generation for digital circuits, Proceedings of the 1997 ACM symposium on Applied computing, p.228-232, April 1997, San Jose, California, United States
	E. M. Rudnick , R. Vietti , A. Ellis , F. Corno , P. Prinetto , M. Sonza Reorda, Fast sequential circuit test generation using high-level and gate-level techniques, Proceedings of the conference on Design, automation and test in Europe, p.570-576, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Irith Pomeranz , Sudhakar M. Reddy, On generating compact test sequences for synchronous sequential circuits, Proceedings of the conference on European design automation, p.105-110, September 18-22, 1995, Brighton, England
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, K2: an estimator for peak sustainable power of VLSI circuits, Proceedings of the 1997 international symposium on Low power electronics and design, p.178-183, August 18-20, 1997, Monterey, California, United States
	David J. Kasik , Harry G. George, Toward automatic generation of novice user test scripts, Proceedings of the SIGCHI conference on Human factors in computing systems: common ground, p.244-251, April 13-18, 1996, Vancouver, British Columbia, Canada
	Irith Pomeranz , Sudhakar M. Reddy, On static compaction of test sequences for synchronous sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.215-220, June 03-07, 1996, Las Vegas, Nevada, United States
	Kwang-Ting Cheng, Gate-level test generation for sequential circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.405-442, Oct. 1996
	D. Kagaris , S. Tragoudas, Von Neumann hybrid cellular automata for generating deterministic test sequences, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.308-321, July 2001
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Dynamic state traversal for sequential circuit test generation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.548-565, July 2000
	Elizabeth M. Rudnick , Janak H. Patel, Simulation-based techniques for dynamic test sequence compaction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.67-73, November 10-14, 1996, San Jose, California, United States
	Daniel G. Saab , Youssef G. Saab , Jacob A. Abraham, Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.40-43, November 06-10, 1994, San Jose, California, United States
	Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy, Techniques for improving the efficiency of sequential circuit test generation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.147-151, November 07-11, 1999, San Jose, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, Simulation based test generation for scan designs, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Raimund Ubar , Jaan Raik, Testing strategies for networks on chip, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Irith Pomeranz , Sudhakar M. Reddy, A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n$n$-Detections in Combinational Circuits, IEEE Transactions on Computers, v.48 n.10, p.1145-1152, October 1999
	Irith Pomeranz , Sudhakar M. Reddy, Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.6, p.596-607, June 2000
	R. Ubar , J. Raik , T. Evartson , M. Kruus , H. Lensen, Diagnostic modelling of digital systems with multi-level decision diagrams, Proceedings of the 17th IASTED international conference on Modelling and simulation, p.207-212, May 24-26, 2006, Montreal, Canada
	Jano I. van Hemert, Evolving combinatorial problem instances that are difficult to solve, Evolutionary Computation, v.14 n.4, p.433-462, December 2006
	Irith Pomeranz , Sudhakar M. Reddy, On test generation by input cube avoidance, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Peter A. Krauss , Andreas Ganz , Kurt J. Antreich, Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.11 n.3, p.227-245, Dec. 1997
	Jaan Raik , Raimund Ubar, Sequential circuit test generation using decision diagram models, Proceedings of the conference on Design, automation and test in Europe, p.145-es, January 1999, Munich, Germany
	Yanti Santoso , Matthew Merten , Elizabeth M. Rudnick , Miron Abramovici, FreezeFrame: compact test generation using a frozen clock strategy, Proceedings of the conference on Design, automation and test in Europe, p.147-es, January 1999, Munich, Germany
	Martin Keim , Nicole Drechsler , Rolf Drechsler , Bernd Becker, Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.17 n.1, p.37-51, February 2001
	Jaan Raik , Raimund Ubar, Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations, Journal of Electronic Testing: Theory and Applications, v.16 n.3, p.213-226, June 2000
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Sequential Circuit Test Generation Using Dynamic State Traversal, Proceedings of the 1997 European conference on Design and Test, p.22, March 17-20, 1997
	I. Pomeranz , S. M. Reddy, On improving genetic optimization based test generation, Proceedings of the 1997 European conference on Design and Test, p.506, March 17-20, 1997
	F. Corno , P. Prinetto , M. Rebaudengo , M. Sonza Reorda, GARDA: a diagnostic ATPG for large synchronous sequential circuits, Proceedings of the 1995 European conference on Design and Test, p.267, March 06-09, 1995
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Alternating Strategies for Sequential Circuit ATPG, Proceedings of the 1996 European conference on Design and Test, p.368, March 11-14, 1996
	F. Corno , P. Prinetto , M. Rebaudengo , M. Sonza Reorda , R. Mosca, Advanced Techniques for GA-based sequential ATPGs, Proceedings of the 1996 European conference on Design and Test, p.375, March 11-14, 1996
	Wei Zhao , C. A. Papachristou, An evolution programming approach on multiple behaviors for the design of application specific programmable processors, Proceedings of the 1996 European conference on Design and Test, p.144, March 11-14, 1996
	Jaan Raik , Raimund Ubar , Taavi Viilukas , Maksim Jenihhin, Mixed hierarchical-functional fault models for targeting sequential cores, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.465-477, March, 2008
	Irith Pomeranz , Sudhakar M. Reddy, Dynamic test compaction for a random test generation procedure with input cube avoidance, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan