Acyclic multi-way partitioning of Boolean networks

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Acyclic multi-way partitioning of Boolean networks

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 670 - 675

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Jason Cong	Department of Computer Science, University of California, Los Angeles, CA
Zheng Li	Department of Computer Science, University of California, Los Angeles, CA
Rajive Bagrodia	Department of Computer Science, University of California, Los Angeles, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 19

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 19

	Amir H. Salek , Jinan Lou , Massoud Pedram, A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together, Proceedings of the 35th annual conference on Design automation, p.128-134, June 15-19, 1998, San Francisco, California, United States
	Jason Cong , Sung Kyu Lim, Performance driven multiway partitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.441-446, January 2000, Yokohama, Japan
	Roman Kužnar , Baldomir Zajc , Franc Brglez, A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions, Proceedings of the conference on European design automation, p.271-276, September 19-23, 1994, Grenoble, France
	Yu-an Chen , Vikas Jha , Rajive Bagrodia, A multidimensional study on the feasibility of parallel switch-level circuit simulation, ACM SIGSIM Simulation Digest, v.27 n.1, p.46-54, July 1997
	Y.-M. Jiang , K.-T. Cheng, Exact and approximate estimation for maximum instantaneous current of CMOS circuits, Proceedings of the conference on Design, automation and test in Europe, p.698-703, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Rajive L. Bagrodia, Perils and pitfalls of parallel discrete-event simulation, Proceedings of the 28th conference on Winter simulation, p.136-143, December 08-11, 1996, Coronado, California, United States
	Jason Cong , Yean-Yow Hwang, Simultaneous depth and area minimization in LUT-based FPGA mapping, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.68-74, February 12-14, 1995, Monterey, California, United States
	Rajive Bagrodia , Zheng Li , Vikas Jha , Yuan Chen , Jason Cong, Parallel logic level simulation of VLSI circuits, Proceedings of the 26th conference on Winter simulation, p.1354-1361, December 11-14, 1994, Orlando, Florida, United States
	Rajive Bagrodia , Yu-an Chen , Vikas Jha , Nicki Sonpar, Parallel gate-level circuit simulation on shared memory architectures, ACM SIGSIM Simulation Digest, v.25 n.1, p.170-174, July 1995
	Jason Cong , Honching Peter Li , Sung Kyu Lim , Toshiyuki Shibuya , Dongmin Xu, Large scale circuit partitioning with loose/stable net removal and signal flow based clustering, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.441-446, November 09-13, 1997, San Jose, California, United States
	Dirk Behrens , Klaus Harbich , Erich Barke, Hierarchical partitioning, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.470-477, November 10-14, 1996, San Jose, California, United States
	Yu-an Chen , Rajive Bagrodia, Shared memory implementation of a parallel switch-level circuit simulator, ACM SIGSIM Simulation Digest, v.28 n.1, p.134-141, July 1998
	Jason Cong , Wilburt Labio , Narayanan Shivakumar, Multi-way VLSI circuit partitioning based on dual net representation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.56-62, November 06-10, 1994, San Jose, California, United States
	Eric S. H. Wong , Evangeline F. Y. Young , W. K. Mak, Clustering based acyclic multi-way partitioning, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Venkatram Krishnaswamy , Prithviraj Banerjee, Actor based parallel VHDL simulation using time warp, ACM SIGSIM Simulation Digest, v.26 n.1, p.135-142, July 1996
	Frank M. Johannes, Partitioning of VLSI circuits and systems, Proceedings of the 33rd annual conference on Design automation, p.83-87, June 03-07, 1996, Las Vegas, Nevada, United States
	Navin Vemuri , Priyank Kalla , Russell Tessier, BDD-based logic synthesis for LUT-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.501-525, October 2002
	Chi-Shong Wang , Chingwei Yeh, Performance-driven technology mapping with MSG partition and selective gate duplication, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.953-973, October 2006
	Kai Zhu, Post-route LUT output polarity selection for timing optimization, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA