A gate-delay model for high-speed CMOS circuits

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A gate-delay model for high-speed CMOS circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 576 - 580

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Florentin Dartu	Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas
Noel Menezes	Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas
Jessica Qian	Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas
Lawrence T. Pillage	Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 17, Downloads (12 Months): 95, Citation Count: 30

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	8	L.T. Pillage and R.A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, April, 1990.
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	12	L.M. Brocco, S.E Mccormick and J. Allen, "Macromodeling CMOS circuits for timing simulation," IEEE Trans. Computer-AidedDesign, December 1988.

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	Akio Hirata , Hidetoshi Onodera , Keikichi Tamaru, Proposal of a timing model for CMOS logic gates driving a CRC &pgr; load, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.537-544, November 08-12, 1998, San Jose, California, United States
	Rohini Gupta , Byron Krauter , Bogdan Tutuianu , John Willis , Lawrence T. Pileggi, The Elmore delay as bound for RC trees with generalized input signals, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.364-369, June 12-16, 1995, San Francisco, California, United States
	Soha Hassoun, Critical path analysis using a dynamically bounded delay model, Proceedings of the 37th conference on Design automation, p.260-265, June 05-09, 2000, Los Angeles, California, United States
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	Lawrence Pileggi, Timing metrics for physical design of deep submicron technologies, Proceedings of the 1998 international symposium on Physical design, p.28-33, April 06-08, 1998, Monterey, California, United States
	Lawrence Pileggi, Coping with RC(L) interconnect design headaches, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.246-253, November 05-09, 1995, San Jose, California, United States
	U. Fassnacht , J. Schietke, Timing analysis and optimization of a high-performance CMOS processor chipset, Proceedings of the conference on Design, automation and test in Europe, p.325-330, February 23-26, 1998, Le Palais des Congrés de Paris, France
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	Lauren Hui Chen , Malgorzata Marek-Sadowska , Forrest Brewer, Buffer delay change in the presence of power and ground noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.461-473, June 2003
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	Brajesh Kumar Kaushik , Sankar Sarkar , R. P. Agarwal, Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load, Integration, the VLSI Journal, v.40 n.4, p.394-405, July, 2007
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