Path hashing to accelerate delay fault simulation

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Path hashing to accelerate delay fault simulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 522 - 526

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Manfred Henftling	Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 80290 Munich, Germany
Hannes C. Wittmann	Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 80290 Munich, Germany
Kurt J. Antreich	Institute of Electronic Design Automation, Department of Electrical Engineering, Technical University of Munich, 80290 Munich, Germany

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Z. Barzilai and B. K. Rosen. "Comparison of AC Self- Testing Procedures". In Proceedings IEEE International Test Co@fence, pages 89-94, October 1983.
	2	G. L. Smith. "Model for Delay Faults Based Upon Paths". Proceedings IEEE International Test Co@fence, pages 342-349, September 1985.
	3	F. Fink , K. Fuchs , M. H. Schulz, Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns, IEEE Transactions on Computers, v.41 n.12, p.1527-1536, December 1992 [doi>10.1109/12.214661]
	4	J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. "Fault Simulation for Structured VLSI". VLSI Systems Design, pages 20-32, December 1985.
	5	Kurt J. Antreich and Michael H. Schulz. "Accelerated Fault Simulation and Fault Grading in Combinational Circuits". IEEE Transactions on Computer-Aided Design, pages 704-712, September 1987.
	6	M. Schulz , F. Fink , K. Fuchs, Parallel pattern fault simulation of path delay faults, Proceedings of the 26th ACM/IEEE conference on Design automation, p.357-363, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74442]
	7	S. Koeppe. "Modeling and Simulation of Delay Faults in CMOS Logic Circuits". In Proceedings IEEE International Test Conference, pages 530-536, September 1986.
	8	Irith Pomeranz , Sudhakar M. Reddy, An efficient non-enumerative method to estimate path delay fault coverage, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.560-567, November 1992, Santa Clara, California, United States
	9	Irith Pomeranz , Sudhakar M. Reddy, An efficient non-enumerative method to estimate path delay fault coverage, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.560-567, November 1992, Santa Clara, California, United States
	10	Irith Pomeranz , Lakshmi N. Reddy , Sudhakar M. Reddy, SPADES: a simulator for path delay faults in sequential circuits, Proceedings of the conference on European design automation, p.428-435, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	11	S. Bose, P. Agrawal, and V. D. Agrawal. "A Path Delay Fault Simulator for Sequential Circuits". In Sixth International Conference on VLSI Design, pages 269- 274, January 1993.
	12	Hannes C. Wittmann and Manfred Henftling. "Efficient Path Identification for Delay Testing Time and Space Optimization". In Proceedings European Test Conference, February 1994. in press.
	13	Karl Fuchs, Franz Fink, and Michael H. Schulz. "DY- NAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults". IEEE Transactions on Computer-Aided Design, pages 1323-1335, October 1991. volume = Vol. CAD-10, number = No. 10.
	14	Franc Brglez and Hideo Fujiwara. "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran". In IEEE International Symposiam on Circuits and Systems; Special Session S6AB on ATPG and Fault Simulation, pages 663-698, June 1985.
	15	Franc Brglez, David Bryan, and Krzysztof Kozminski. "Combinational Profiles of Sequential Benchmark Circuits". In Proceedings IEEE International Symposium on Circuits and Systems, pages 1929-1934, May 1989.
	16	Franc Brglez. "ACM/SIGDA Benchmark Electronic Newsletter DAC '93 Edition, June 1993.

CITED BY 3

	U. Sparmann , D. Luxenburger , K.-T. Cheng , S. M. Reddy, Fast identification of robust dependent path delay faults, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.119-125, June 12-16, 1995, San Francisco, California, United States
	Frank Pöhl , Walter Anheier, Quality Determination for Gate Delay Fault Tests Considering Three-State Elements, Journal of Electronic Testing: Theory and Applications, v.14 n.1-2, p.49-55, Feb./April 1999
	M. Henftling , H. Wittman, Bit parallel test pattern generation for path delay faults, Proceedings of the 1995 European conference on Design and Test, p.521, March 06-09, 1995