Performance analysis and optimization of schedules for conditional and loop-intensive specifications

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Performance analysis and optimization of schedules for conditional and loop-intensive specifications

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 491 - 496

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Subhrajit Bhattacharya	Dept. of Computer Science, Duke University, Durham, NC and CCRI, NEC
Sujit Dey	C&C Research Labs, NEC, Princeton, NJ
Franc Brglez	CBL, Dept. of ECE, North Carolina State Univ., Raleigh, NC

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 9, Citation Count: 28

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 28

	Ganesh Lakshminarayana , Kamal S. Khouri , Niraj K. Jha, Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.244-250, November 09-13, 1997, San Jose, California, United States
	Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha, Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.577-584, November 08-12, 1998, San Jose, California, United States
	Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno , Alberto Sangiovanni-Vincentelli, A case study on modeling shared memory access effects during performance analysis of HW/SW systems, Proceedings of the 6th international workshop on Hardware/software codesign, p.117-121, March 15-18, 1998, Seattle, Washington, United States
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Fast high-level power estimation for control-flow intensive design, Proceedings of the 1998 international symposium on Low power electronics and design, p.299-304, August 10-12, 1998, Monterey, California, United States
	Ganesh Lakshminarayana , Niraj K. Jha, FACT: a framework for the application of throughput and power optimizing transformations to control-flow intensive behavioral descriptions, Proceedings of the 35th annual conference on Design automation, p.102-107, June 15-19, 1998, San Francisco, California, United States
	Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha, Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions, Proceedings of the 35th annual conference on Design automation, p.108-113, June 15-19, 1998, San Francisco, California, United States
	K. S. Khouri , G. Lakshminarayana , N. K. Jha, IMPACT: a high-level synthesis system for low power control-flow intensive circuits, Proceedings of the conference on Design, automation and test in Europe, p.848-854, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Sujit Dey , Surendra Bommu, Performance analysis of a system of communicating processes, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.590-597, November 09-13, 1997, San Jose, California, United States
	Subhrajit Bhattacharya , Sujit Dey , Franc Breglez, Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.2, p.285-307, April 1998
	Maher Rahmouni , Ahmed A. Jerraya, Formulation and evaluation of scheduling techniques for control flow graphs, Proceedings of the conference on European design automation, p.386-391, September 18-22, 1995, Brighton, England
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Memory binding for performance optimization of control-flow intensive behaviors, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.482-488, November 07-11, 1999, San Jose, California, United States
	Indradeep Ghosh , Sujit Dey , Niraj K. Jha, A fast and low cost testing technique for core-based system-on-chip, Proceedings of the 35th annual conference on Design automation, p.542-547, June 15-19, 1998, San Francisco, California, United States
	Abhijit K. Deb , Johnny Öberg , Axel Jantsch, Control and communication performance analysis of embedded DSP systems in the MASIC methodology, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Fast performance analysis of bus-based system-on-chip communication architectures, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.566-573, November 07-11, 1999, San Jose, California, United States
	Per Bjuréus , Axel Jantsch, Performance analysis with confidence intervals for embedded software processes, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Glitch analysis and reduction in register transfer level power optimization, Proceedings of the 33rd annual conference on Design automation, p.331-336, June 03-07, 1996, Las Vegas, Nevada, United States
	S. Narayan , D. Gajski, Rapid performance estimation for system design, Proceedings of the conference on European design automation, p.206-211, September 1996, Geneva, Switzerland
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
	Vijay Raghunathan , Srivaths Ravi , Anand Raghunathan , Ganesh Lakshminarayana, Transient power management through high level synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	W. Wang , T. K. Tan , J. Luo , Y. Fei , L. Shang , K. S. Vallerio , L. Zhong , A. Raghunathan , N. K. Jha, A comprehensive high-level synthesis system for control-flow intensive behaviors, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Anand Raghunathan , Sujit Dey , Niraj K. Jha, High-level macro-modeling and estimation techniques for switching activity and power consumption, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.538-557, August 2003
	Kai Kapp , Viktor Sabelfeld, Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Memory binding for performance optimization of control-flow intensive behavioral descriptions, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.513-524, May 2005
	Jason Cong , Zhiru Zhang, An efficient and versatile scheduling algorithm based on SDC formulation, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Aravind Vijayakumar , F. Brewer, Weighted control scheduling, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.777-783, November 06-10, 2005, San Jose, CA
	Srivaths Ravi , Indradeep Ghosh , Rabindra K. Roy , Sujit Dey, Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.201-212, Oct. 1998
	M. Rahmouni , A. A. Jerraya, PPS: a pipeline path-based scheduler, Proceedings of the 1995 European conference on Design and Test, p.557, March 06-09, 1995
	Vijay Raghunathan , Mani B. Srivastava , Milos D. Ercegovac , Anand Raghunathan, High-Level Synthesis with SIMD Units, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.407, January 07-11, 2002