| Random generation of test instances for logic optimizers |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 31st annual Design Automation Conference
table of contents
San Diego, California, United States
Pages: 430 - 434
Year of Publication: 1994
ISBN:0-89791-653-0
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Authors
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Kazuo Iwama
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Department of Computer Science and Communication Engineering, Kyushu University, Hakozaki, Fukuoka 812, Japan
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Kensuke Hino
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Department of Computer Science and Communication Engineering, Kyushu University, Hakozaki, Fukuoka 812, Japan
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 7
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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R. K. BRAYTON, R. RUDELL, A. L. SANGIOVANNI- VINCENTELLI, AND A. R. WANG, "Mis: A multiplelevel logic optimization system," IEEE Trans. CAD, 6, pp. 1062-1081, 1987.
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K. HINO AND K. IWAMA,"On a complete set of basic operations to transform between equivalent switching circuit," Technical Report of the Institute of Electronics, Information and Communication Engineers, COMP92-67 (1992-11) (i. J~p~.~).
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Kazuo Iwama , Hidetoshi Abeta , Eiji Miyano, Random Generation of Satisfiable and Unsatisfiable CNF Predicates, Proceedings of the IFIP 12th World Computer Congress on Algorithms, Software, Architecture - Information Processing '92, Volume 1, p.322-328, September 07-11, 1992
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D. MITCHELL, B. SELMAN, AND H. LEVESQUE, "Hard and easy distributions of SAT problems," in Proc. 10th National Conference on Artificial Intelligence, pp. 459- 465, 1992.
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E. M. SENTOVICH, K. J. SINGH, et al., "SIS: A system for sequential circuit synthesis," Memorandum No. UCB/ERL M92/41, 1992.
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G. TINHOFER, "Generating graphs uniformly at random," in Computational graph theory, pp. 235-255, Springer, 1990.
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S. YANG, "Logic synthesis and optimization Benchmarks user guide version 3.0," in 1991 MCNC International Workshop on Logic Synthesis.
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CITED BY 7
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D. Ghosh , N. Kapur , J. Harlow, III , F. Brglez, Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking, Proceedings of the conference on Design, automation and test in Europe, p.656-663, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Boris Ratchev , Mike Hutton , Gregg Baeckler , Babette van Antwerpen, Verifying the correctness of FPGA logic synthesis algorithms, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
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