Performance optimization using exact sensitization

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Performance optimization using exact sensitization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 425 - 429

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Alexander Saldanha	Cadence Berkeley Labs, Berkeley, CA
Heather Harkness	Digital Equipment Corporation, Hudson, MA and University of California, Berkeley, CA
Patrick C. McGeer	Cadence Berkeley Labs, Berkeley, CA
Robert K. Brayton	University of California, Berkeley, CA
Alberto L. Sangiovanni-Vincentelli	University of California, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Pranav Ashar , Sujit Dey , Sharad Malik, Exploiting multi-cycle false paths in the performance optimization of sequential circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.510-517, November 1992, Santa Clara, California, United States
	2	H.-C. Chen , D. H. C. Du , S. W. Cheng, Circuit enhancement by eliminating long false paths, Proceedings of the 29th ACM/IEEE conference on Design automation, p.249-252, June 08-12, 1992, Anaheim, California, United States
	3	H. Chen, D. Du, and L-R. Liu. Critical path selection for performance optimization. In IEEE Transactions on Computer-Aided Design, pages 165-195, February 1993.
	4	E McGeer, R. Brayton, A. Sangiovanni-Vincentelli, and S. Sahni. Performance enhancement through the generalized bypass transform. In Proceedings of the International Conference on Computer-Aided Design, pages 184-187, November 1991.
	5	E McGeer, A. Saldanha, E Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. Timing analysis and delay-fault test generation using path recursive functions. In Proceedings of the International Conference on Computer-AidedDesign, pages 180-183, November 1991.
	6	A. Saldanha , R. K. Brayton , A. L. Sangiovanni-Vincentelli, Circuit structure relations to redundancy and delay: the KMS algorithm revisited, Proceedings of the 29th ACM/IEEE conference on Design automation, p.245-248, June 08-12, 1992, Anaheim, California, United States
	7	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	8	Kanwar Jit Singh, Performance optimization of digital circuits, University of California at Berkeley, Berkeley, CA, 1992
	9	K. Singh, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Timing optimization of combinational logic. In Proceedings of the International Conference on Computer-AidedDesign, pages 282-285, November 1988.
	10	H. Touati and R.K. Brayton. Computing the initial states of retimed circuits. IEEE Transactions on Computer-Aided Design, July 1992.
	11	H. Touati, H. Savoj, and R. Brayton. Delay optimization of combinational logic circuits through clustering and partial collapsing. In Proceedings of the International Conference on Computer-Aided Design, pages 188-191, November 1991.

CITED BY 5

	Rajat Aggarwal , Rajeev Murgai , Masahiro Fujita, Speeding up technology-independent timing optimization by network partitioning, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.83-90, November 09-13, 1997, San Jose, California, United States
	Berhard Rohfleisch , Bernd Wurth , Kurt Antreich, Logic clause analysis for delay optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.668-672, June 12-16, 1995, San Francisco, California, United States
	Joel Grodstein , Eric Lehman , Heather Harkness , Bill Grundmann , Yosinatori Watanabe, A delay model for logic synthesis of continuously-sized networks, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.458-462, November 05-09, 1995, San Jose, California, United States
	Ankur Srivastava , Ryan Kastner , Chunhong Chen , Majid Sarrafzadeh, Timing driven gate duplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.42-51, January 2004
	Cristian Soviani , Olivier Tardieu , Stephen A. Edwards, Optimizing sequential cycles through Shannon decomposition and retiming, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany