Optimum functional decomposition using encoding

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Optimum functional decomposition using encoding

Full text

Pdf (209 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 408 - 414

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Rajeev Murgai	Department of EECS, University of California, Berkeley, CA
Robert K. Brayton	Department of EECS, University of California, Berkeley, CA
Alberto Sangiovanni-Vincentelli	Department of EECS, University of California, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 9, Citation Count: 14

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/196244.196440 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. L. Ashenhurst, "The Decomposition of Switching Functions", Proc. of International Symp on Theory of Switching Functions, 1959.
	2	J.P. Roth and R.M. Karp, "Minimization over Boolean graphs", IBM Journal of Research and Development, April 1962.
	3	Xilinx Inc., 2069, Hamilton Ave. San Jose, CA-95125, The Programmable Gate Array Data Book.
	4	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	5	R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic Optimization System", IEEE Transactions on CAD, November 1987.
	6	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	7	Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, Proceedings of the 30th international conference on Design automation, p.642-647, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165078]
	8	G. De Micheli, R. K. Brayton, and A. Sangiovanni- Vincentelli, "Optimal state assignment for finite state machines", IEEE Transactions on Computer-Aided Design, July 1985.
	9	G. De Micheli, "Symbolic design of combinational and sequential logic circuits implemented by two-level logic macros", IEEE Transactions on Computer-Aided Design, Oct. 1986.
	10	S. Devadas and R. Newton, "Exact algorithms for output encoding, state assignment and four-level Boolean minimization", IEEE Transactions on Computer-Aided Design, Jan 1991.
	11	Alexander Saldanha , Tiziano Villa , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, A framework for satisfying input and output encoding constraints, Proceedings of the 28th conference on ACM/IEEE design automation, p.170-175, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127656]
	12	A. Saldanha , A. R. Wang , R. K. Brayton , A. L. Sangiovanni-Vincentelli, Multi-level logic simplification using don't cares and filters, Proceedings of the 26th ACM/IEEE conference on Design automation, p.277-282, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74429]
	13	L. Lavagno, T. Villa and A. Sangiovanni-Vincentelli, "Advances in encoding for logic synthesis", In Progress in Compurer Aided VLSI design, G. Zobrist ed., in press, Ablex, Norwood, 1992.
	14	S. Yang and M. Ciesielski, "Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization", IEEE Transactions on Computer-Aided Design, January, 1991.
	15	T. Villa and A. Sangiovanni-Vincentelli, "NOVA: State Assignment for optimal two-level logic implementations", IEEE Transactions on Computer-Aided Design, Sept. 1990.
	16	B. Lin, and A. R. Newton, "Synthesis of multiple level logic from symbolic high-level description languages", Proc. of the International Conference on VLSL Munich, 1989.
	17	R.L. Rudell, "Logic Synthesis for VLSI Design", UCB/ERL Memorandum M89/~9, April 1989.

CITED BY 14

	Victor N. Kravets , Karem A. Sakallah, Constructive library-aware synthesis using symmetries, Proceedings of the conference on Design, automation and test in Europe, p.208-215, March 27-30, 2000, Paris, France
	Bernd Wurth , Klaus Eckl , Kurt Antreich, Functional multiple-output decomposition: theory and an implicit algorithm, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.54-59, June 12-16, 1995, San Francisco, California, United States
	Jian Qiao , Makoto Ikeda , Kunihiro Asada, Finding an optimal functional decomposition for LUT-based FPGA synthesis, Proceedings of the 2001 conference on Asia South Pacific design automation, p.225-230, January 2001, Yokohama, Japan
	Victor N. Kravets , Karem A. Sakallah, Resynthesis of multi-level circuits under tight constraints using symbolic optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.687-693, November 10-14, 2002, San Jose, California
	Ted Stanion , Carl Sechen, A method for finding good Ashenhurst decompositions and its application to FPGA synthesis, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.60-64, June 12-16, 1995, San Francisco, California, United States
	Juinn-Dar Huang , Jing-Yang Jou , Wen-Zen Shen, Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.359-363, November 05-09, 1995, San Jose, California, United States
	Jie-Hong R. Jiang , Jing-Yang Jou , Juinn-Dar Huang, Compatible class encoding in hyper-function decomposition for FPGA synthesis, Proceedings of the 35th annual conference on Design automation, p.712-717, June 15-19, 1998, San Francisco, California, United States
	Hiroshi Sawada , Takayuki Suyama , Akira Nagoya, Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.353-358, November 05-09, 1995, San Jose, California, United States
	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Bernd Wurth , Ulf Schlichtmann , Klaus Eckl , Kurt J. Antreich, Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.3, p.313-350, July 1999
	Lech Jóźwiak , Aleksander S´lusarczyk, General decomposition of incompletely specified sequential machines with multi-state behavior realization, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.8, p.445-492, August 2004
	Alan Mishchenko , Xinning Wang , Timothy Kam, A new enhanced constructive decomposition and mapping algorithm, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Christian Legl , Bernd Wurth , Klaus Eckl, An Implicit Algorithm for Support Minimization during Functional Decomposition, Proceedings of the 1996 European conference on Design and Test, p.412, March 11-14, 1996
	B. Ye. Rytsar , A. B. Kmet', A New Method of Coding Minorants in Problems of Synthesis of Digital Devices from PLAs, Cybernetics and Systems Analysis, v.39 n.2, p.212-234, March-April 2003