RC interconnect optimization under the Elmore delay model

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RC interconnect optimization under the Elmore delay model

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 387 - 391

Year of Publication: 1994

ISBN:0-89791-653-0

Author

Sachin S. Sapatnekar

Department of Electrical Engineering and Computer Engineering, Iowa State University, Ames, IA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 35, Citation Count: 27

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Jason Cong , Kwok-Shing Leung , Dian Zhou, Performance-driven interconnect design based on distributed RC delay model, Proceedings of the 30th international conference on Design automation, p.606-611, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165065]
	2	Jason Cong , Kwok-Shing Leung, Optimal wiresizing under the distributed Elmore delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.634-639, November 07-11, 1993, Santa Clara, California, United States
	3	J. Rubenstein, P. Penfield, and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Transactions on Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
	4	S. S. Sapatnekar, "RC interconnect optimization under the Elmore delay model," Tech. Rep. ISU- CPRE-94-SS03, Iowa State University, Ames, IA, 1994.
	5	J. Ecker, "Geometric programming: methods, computations and applications," SIAM Review, vol. 22, pp. 338-362, July 1980.

CITED BY 27

	Jiang Hu , Sachin S. Sapatnekar, Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model, Proceedings of the 1999 international symposium on Physical design, p.133-138, April 12-14, 1999, Monterey, California, United States
	Yu-Min Lee , Hing Yin Lai , Charlie Chung-Ping Chen, Optimal spacing and capacitance padding for general clock structures, Proceedings of the 2001 conference on Asia South Pacific design automation, p.115-119, January 2001, Yokohama, Japan
	Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.478-511, Oct. 1996
	John Lillis , Chung-Kuan Cheng, Timing optimization for multi-source nets: characterization and optimal repeater insertion, Proceedings of the 34th annual conference on Design automation, p.214-219, June 09-13, 1997, Anaheim, California, United States
	Tianxiong Xue , Ernest S. Kuh, Post routing performance optimization via multi-link insertion and non-uniform wiresizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.575-580, November 05-09, 1995, San Jose, California, United States
	Rony Kay , Gennady Bucheuv , Lawrence T. Pileggi, EWA: exact wiring-sizing algorithm, Proceedings of the 1997 international symposium on Physical design, p.178-185, April 14-16, 1997, Napa Valley, California, United States
	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.568-574, November 05-09, 1995, San Jose, California, United States
	Tao Lin , Lawrence T. Pileggi, RC(L) interconnect sizing with second order considerations via posynomial programming, Proceedings of the 2001 international symposium on Physical design, p.16-21, April 01-04, 2001, Sonoma, California, United States
	Chris C. N. Chu , D. F. Wong, Closed form solution to simultaneous buffer insertion/sizing and wire sizing, Proceedings of the 1997 international symposium on Physical design, p.192-197, April 14-16, 1997, Napa Valley, California, United States
	Chung-Ping Chen , Yao-Wen Chang , D. F. Wong, Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation, Proceedings of the 33rd annual conference on Design automation, p.405-408, June 03-07, 1996, Las Vegas, Nevada, United States
	J. Cong , C. Koh , K. Leung, Simultaneous buffer and wire sizing for performance and power optimization, Proceedings of the 1996 international symposium on Low power electronics and design, p.271-276, August 12-14, 1996, Monterey, California, United States
	Chung-Ping Chen , Hai Zhou , D. F. Wong, Optimal non-uniform wire-sizing under the Elmore delay model, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.38-43, November 10-14, 1996, San Jose, California, United States
	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Is wire tapering worthwhile?, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.430-436, November 07-11, 1999, San Jose, California, United States
	Takumi Okamoto , Jason Cong, Buffered Steiner tree construction with wire sizing for interconnect layout optimization, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.44-49, November 10-14, 1996, San Jose, California, United States
	Yehea I. Ismail , Eby G. Friedman , Jose L. Neves, Equivalent Elmore delay for RLC trees, Proceedings of the 36th ACM/IEEE conference on Design automation, p.715-720, June 21-25, 1999, New Orleans, Louisiana, United States
	Noel Menezes , Satyamurthy Pullela , Lawrence T. Pileggi, Simultaneous gate and interconnect sizing for circuit-level delay optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.690-695, June 12-16, 1995, San Francisco, California, United States
	Tianxiong Xue , Ernest S. Kuh, Post routing performance optimization via tapered link insertion and wiresizing, Proceedings of the conference on European design automation, p.74-79, September 18-22, 1995, Brighton, England
	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage, RC interconnect synthesis—a moment fitting approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.418-425, November 06-10, 1994, San Jose, California, United States
	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
	Jiang Hu , Sachin S. Sapatnekar, FAR-DS: full-plane AWE routing with driver sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.84-89, June 21-25, 1999, New Orleans, Louisiana, United States
	Jason Cong , Lei He, An efficient approach to simultaneous transistor and interconnect sizing, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.181-186, November 10-14, 1996, San Jose, California, United States
	Chung-Ping Chen , Chris C. N. Chu , D. F. Wong, Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.617-624, November 08-12, 1998, San Jose, California, United States
	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin , Ching-Yen Ho, New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing, Proceedings of the 33rd annual conference on Design automation, p.395-400, June 03-07, 1996, Las Vegas, Nevada, United States
	Xiaoping Tang , Ruiqi Tian , Hua Xiang , D. F. Wong, A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Ke Cao , Jiang Hu , Mosong Cheng, Wire sizing and spacing for lithographic printability and timing optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.12, p.1332-1340, December 2007