Rectilinear Steiner trees with minimum Elmore delay

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Rectilinear Steiner trees with minimum Elmore delay

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 381 - 386

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Kenneth D. Boese	CS Dept., University of California at Los Angeles, Los Angeles, CA
Andrew B. Kahng	CS Dept., University of California at Los Angeles, Los Angeles, CA
Bernard A. McCoy	CS Dept., University of Virginia, Charlottesville, VA
Gabriel Robins	CS Dept., University of Virginia, Charlottesville, VA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 11

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. J. Alpert, T. C. Hu, J. H. Huang and A. B. Kahng, "A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Global Routing", technical report CSD-920051, UCLA Department of Computer Science, 1992.
	2	Kenneth D. Boese , Andrew B. Kahng , Gabriel Robins, High-performance routing trees with identified critical sinks, Proceedings of the 30th international conference on Design automation, p.182-187, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164662]
	3	K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Fidelity and Near-Optimality of Elmore-Based Routing Constructions", Proc. IEEE Intl. Conf. on Computers and Processors, October 1993, pp. 81-84.
	4	K.D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Near- Optimal Critical Sink Routing Tree Constructions", technical report TR-930027, UCLA CS Department, 1993.
	5	James P. Cohoon , L. J. Randall, Critical Net Routing, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.174-177, October 14-16, 1991
	6	J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh, and C. K. Wong, "Provably Good Performance-Driven Global Routing", IEEE Trans. on CAD 11(6), June 1992, pp. 739-752.
	7	Jason Cong , Kwok-Shing Leung , Dian Zhou, Performance-driven interconnect design based on distributed RC delay model, Proceedings of the 30th international conference on Design automation, p.606-611, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165065]
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	10	W. C. Elmore, "The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifiers", J. Applied Physics 19 (1948), pp. 55-63.
	11	M. Hanan, "On Steiner's Problem with Rectilinear Distance", SIAM J. Appl. Math., 14 (1966), pp. 255-265.
	12	A. B. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics with Good Performance", IEEE Transactions on CAD 11(7), July 1992, pp. 893-902.
	13	S. Kim , R. M. Owens , M. J. Irwin, Experiments with a performance driven module generator, Proceedings of the 29th ACM/IEEE conference on Design automation, p.687-690, June 08-12, 1992, Anaheim, California, United States
	14	A. Prim, "Shortest Connecting Networks and Some Generalizations", Bell System Tech. J. 36 (1957), pp. 1389-1401.
	15	S. K. Rao, P. Sadayappan, F. K. Hwang and P. W. Shor, "The Rectilinear Steiner Arborescence Problem", Algorithmica 7 (1992), pp. 277-288.
	16	J. Rubinstein, P. Penfield, and M. A. Horowitz, "Signal Delay in RC Tree Networks", IEEE Trans. on CAD 2(3) (1983), pp. 202-211.
	17	Suphachai Sutanthavibul , Eugene Shragowitz, An adaptive timing-driven layout for high speed VLSI, Proceedings of the 27th ACM/IEEE conference on Design automation, p.90-95, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123233]
	18	R. S. Tsay, "Exact Zero Skew", Proc. IEEE Intl. Conference on Computer-Aided Design, 1991, pp. 336-339.
	19	J. Vlach, J. A. Barby, A. Vannelli, T. Talkhan and C. J. Shi, "Group Delay as an Estimate of Delay in Logic", IEEE Transactions on Computer-Aided Design, 10(7), 1991, pp. 949-953.

CITED BY 11

	Tianxiong Xue , Ernest S. Kuh, Post routing performance optimization via multi-link insertion and non-uniform wiresizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.575-580, November 05-09, 1995, San Jose, California, United States
	D. Wang , E. S. Kuh, A performance-driven MCM router with special consideration of crosstalk reduction, Proceedings of the conference on Design, automation and test in Europe, p.466-470, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Ashok Vittal , Malgorzata Marek-Sadowska, Power distribution topology design, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.503-507, June 12-16, 1995, San Francisco, California, United States
	Bharat Krishna , C. Y. Roger Chen , Naresh K. Sehgal, A novel technique for sea of gates global routing, Proceedings of the 10th Great Lakes symposium on VLSI, p.71-74, March 02-04, 2000, Chicago, Illinois, United States
	Yukiko Kubo , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani, Self-reforming routing for stochastic search in VLSI interconnection layout, Proceedings of the 2000 conference on Asia South Pacific design automation, p.87-92, January 2000, Yokohama, Japan
	Noel Menezes , Satyamurthy Pullela , Lawrence T. Pileggi, Simultaneous gate and interconnect sizing for circuit-level delay optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.690-695, June 12-16, 1995, San Francisco, California, United States
	Maggie Kang , Wayne W.-M. Dai , Tom Dillinger , David LaPotin, Delay bounded buffered tree construction for timing driven floorplanning, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.707-712, November 09-13, 1997, San Jose, California, United States
	LiYi Lin , YiYu Liu , Ting Ting Hwang, A construction of minimal delay Steiner tree using two-pole delay model, Proceedings of the 2001 conference on Asia South Pacific design automation, p.126-132, January 2001, Yokohama, Japan
	Tianxiong Xue , Ernest S. Kuh, Post routing performance optimization via tapered link insertion and wiresizing, Proceedings of the conference on European design automation, p.74-79, September 18-22, 1995, Brighton, England
	Sven Peyer , Martin Zachariasen , David Grove Jørgensen, Delay-related secondary objectives for rectilinear Steiner minimum trees, Discrete Applied Mathematics, v.136 n.2-3, p.271-298, 15 February 2004
	Huibo Hou , Sachin S. Sapatnekar, Routing tree topology construction to meet interconnect timing constraints, Proceedings of the 1998 international symposium on Physical design, p.205-210, April 06-08, 1998, Monterey, California, United States