An efficient zero-skew routing algorithm

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An efficient zero-skew routing algorithm

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 375 - 380

Year of Publication: 1994

ISBN:0-89791-653-0

Author

Masato Edahiro

C&C Research Laboratories, NEC Corporation, Miyazaki, Miyamae-ku, Kawasaki 216, Japan and Department of Computer Science, Princeton University, Princeton, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 36, Citation Count: 16

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Alfred V. Aho , John E. Hopcroft, The Design and Analysis of Computer Algorithms, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1974
	2	T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahng, "Zero skew clock routing with minimum wirelength," IEEE Trans. on CAS II, Vol. 39, pp.799-814, 1992.
	3	J. C. Cong, A. B. Kahng, and G. Robins, "Matching-based methods for high-performance clock routing," IEEE Trans. on CAD, Vol. 12, pp.1157-1169, 1993.
	4	Masato Edahiro, A clustering-based optimization algorithm in zero-skew routings, Proceedings of the 30th international conference on Design automation, p.612-616, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165066]
	5	M. Edahiro, "Delay minimization for zero-skew routing," Proc. of 1993 ICCAD, pp.563-566, 1993.
	6	M. Edahiro, "Equi-spreading tree in Manhattan distance," unpublished.
	7	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	8	Ying-Meng Li , Marwan A. Jabri, A zero-skew clock routing scheme for VLSI circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.458-463, November 1992, Santa Clara, California, United States
	9	Franco P. Preparata , Michael I. Shamos, Computational geometry: an introduction, Springer-Verlag New York, Inc., New York, NY, 1985
	10	Robert Sedgewick, Algorithms in C, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
	11	R. S. Tsay, "An exact zero-skew clock routing algorithm," IEEE Trans. on CAD, Vol. 12, pp.242-249, 1993.

CITED BY 16

	Weixiang Shen , Yici Cai , Xianlong Hong , Jiang Hu , Bing Lu, Zero skew clock routing in X-architecture based on an improved greedy matching algorithm, Integration, the VLSI Journal, v.41 n.3, p.426-438, May, 2008
	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.341-388, July 1998
	Ashok Vittal , Malgorzata Marek-Sadowska, Power optimal buffered clock tree design, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.497-502, June 12-16, 1995, San Francisco, California, United States
	Jatuchai Pangjun , Sachin S. Sapatnekar, Clock distribution using multiple voltages, Proceedings of the 1999 international symposium on Low power electronics and design, p.145-150, August 16-17, 1999, San Diego, California, United States
	Chung-wen Albert Tsao , Cheng-kok Koh, UST/DME: a clock tree router for general skew constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.359-379, July 2002
	Yukiko Kubo , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani, Self-reforming routing for stochastic search in VLSI interconnection layout, Proceedings of the 2000 conference on Asia South Pacific design automation, p.87-92, January 2000, Yokohama, Japan
	Jae W. Chung , De-Yu Kao , Chung-Kuan Cheng , Ting-Ting Lin, Optimization of power dissipation and skew sensitivity in clock buffer synthesis, Proceedings of the 1995 international symposium on Low power design, p.179-184, April 23-26, 1995, Dana Point, California, United States
	Moses Charikar , Jon Kleinberg , Ravi Kumar , Sridhar Rajagopalan , Amit Sahai , Andrew Tomkins, Minimizing wirelength in zero and bounded skew clock trees, Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms, p.177-184, January 17-19, 1999, Baltimore, Maryland, United States
	Dennis J. H. Huang , Andrew B. Kahng , Chung-Wen Albert Tsao, On the bounded-skew clock and Steiner routing problems, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.508-513, June 12-16, 1995, San Francisco, California, United States
	Jatuchai Pangjun , Sachin S. Sapatnekar, Low-power clock distribution using multiple voltages and reduced swings, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.309-318, June 2002
	Chung-Wen Albert Tsao , Cheng-Kok Koh, UST/DME: a clock tree router for general skew constraints, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Shantanu Ganguly , Shervin Hojat, Clock distribution design and verification for PowerPC microprocessors, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.58-61, November 05-09, 1995, San Jose, California, United States
	Rupesh S. Shelar, An efficent clustering algorithm for low power clock tree synthesis, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Saif Ali Butt , Stefan Schmermbeck , Jurij Rosenthal , Alexander Pratsch , Eike Schmidt, System level clock tree synthesis for power optimization, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Wei-Chung Chao , Wai-Kei Mak, Low-power gated and buffered clock network construction, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-20, January 2008
	Rupesh S. Shelar, An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA