Generation of high quality non-robust tests for path delay faults

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Generation of high quality non-robust tests for path delay faults

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 365 - 369

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Kwang-Ting Cheng	Department of ECE, University of California, Santa Barbara, CA
Hsi-Chuan Chen	AT&T Bell Laboratories, Murray Hill, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K. D. Wagner, "The Error Latency of Delay Faults in Combinational and Sequential Circuits," Proc. Int'l Test Conference, pp. 334-341 (Nov. 1985).
	2	J. A. Waicukauski, E. Lindbloom, B. Rosen, and V. Iyengar, "Transition Fault Simulation," IEEE Design and Test, pp. 32-38 (April 1987).
	3	J. P. Lesser and J. J. Shedletsky, "An Experimental delay test generator for LSI logic," IEEE Trans. on Computers, pp. 235-248 (March 1980).
	4	G. L. Smith, "Model for Delay Faults Based upon Paths," Proc. IEEE Int'l Test Conf., pp. 342-349 (Nov. 1985).
	5	C. J. Lin and S. M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Trans. on Computer-Aided Design, pp. 694-703 (Sept. 1987).
	6	Bernd Könemann , J. Barlow , P. Chang , R. Gabrielson , C. Goertz , Brion L. Keller , Kevin McCauley , J. Tischer , Vijay S. Iyengar , Barry K. Rosen , T. Williams, Delay Test: The Next Frontier for LSSD Test Systems, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.578-587, September 20-24, 1992
	7	K. Fuchs, F. Fink, and M. H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults," IEEE Trans. on CAD CAD-10, pp. 1323- 1335 (Oct. 1991).
	8	Kwang-Ting Cheng , Hsi-Chuan Chen, Delay Testing for Non-Robust Untestable Circuits, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.954-961, October 17-21, 1993
	9	S. M. Reddy, C. J. Lin, and S. Patil, "An Automatic Test Pattern Generator for the Detection of Path Delay Faults," Proc. Int'l Conf. on CAD, pp. 284-287 (Nov. 1987).
	10	H.-C. Chen and D. H.-C. Du, "Path Sensitization in Critical Path Problem," IEEE Transactions on Computer-Aided Design 12-2, pp. 196-207 (Feb. 1993).
	11	S. Patil and S. M. Reddy, "A Test Generation System For Path Delay Faults," Proc. Int. Conf. Computer Design (ICCD-89) , pp. 40-43 (Oct. 1989).
	12	S. Devadas and K. Keutzer, "Synthesis of Robust Delay- Fault Testable Circuits: Theory," IEEE Transactions on Computer-Aided Design 11-1, pp. 87-101 (Jan. 1992).
	13	A. Pramanick and S. M. Reddy, "On The Design of Path Delay Fault Testable Combinational Circuits," Proc. 20th Fault Tolerant Computing Symp., pp. 374-381 (June 1990).
	14	N.K. Jha, I. Pomeranz, S. M. Reddy, and R. J. Miller, "Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability," Proc. Int'l Symp. on Fault-Tolerant Computing, pp. 280-287 (July 1992).
	15	T. Kirkland , M. R. Mercer, A topological search algorithm for ATPG, Proceedings of the 24th ACM/IEEE conference on Design automation, p.502-508, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37963]

CITED BY 4

	U. Sparmann , D. Luxenburger , K.-T. Cheng , S. M. Reddy, Fast identification of robust dependent path delay faults, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.119-125, June 12-16, 1995, San Francisco, California, United States
	Joonyoung Kim , Jesse Whittemore , João P. Marques-Silva , Karem Sakallah, On applying incremental satisfiability to delay fault testing, Proceedings of the conference on Design, automation and test in Europe, p.380-384, March 27-30, 2000, Paris, France
	Thomas M. Storey , Bruce McWilliam, A Test Methodology for High Performance MCMs, Journal of Electronic Testing: Theory and Applications, v.10 n.1-2, p.109-118, Feb./April 1997
	D. Maruyama , A. Kanuma , T. Mochiyama , H. Komatsu , Y. Sugiyama , N. Ito, Detection of multiple transitions in delay fault test of SPARC64 microprocessor, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.893-898, November 07-11, 2004