A methodology and algorithms for post-placement delay optimization

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A methodology and algorithms for post-placement delay optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 327 - 332

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Lalgudi N. Kannan	Escalade Corp., 1210 East Arques Avenue, Sunnyvale, CA and Cadence Design Systems, Inc., 2655 Seely Road, San Jose, CA
Peter R. Suaris	Escalade Corp., 1210 East Arques Avenue, Sunnyvale, CA and Cadence Design Systems, Inc., 2655 Seely Road, San Jose, CA
Hong-Gee Fang	Cadence Design Systems, Inc., 2655 Seely Road MS 6B1, San Jose, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 24

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSL Addison-Wesley, 1990.
	2	P. Abouzeid , K. Sakouti , G. Saucier , F. Poirot, Multilevel synthesis minimizing the routing factor, Proceedings of the 27th ACM/IEEE conference on Design automation, p.365-368, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123307]
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	4	M. Pedram and N. Bhat, "Layout Driven Logic Restructuring/Decomposition," IEEE Intl. Conf. on Computer-Aided Design (ICCAD-91), pp. 134-137, 1991.
	5	Hirendu Vaishnav , Massoud Pedram, Routability-driven fanout optimization, Proceedings of the 30th international conference on Design automation, p.230-235, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164684]
	6	Shen Lin , M. Marek-Sadowska , Ernest S. Kuh, Delay and area optimization in standard-cell design, Proceedings of the 27th ACM/IEEE conference on Design automation, p.349-352, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123301]
	7	Kanwar Jit Singh , Alberto Sangiovanni-Vincentelli, A heuristic algorithm for the fanout problem, Proceedings of the 27th ACM/IEEE conference on Design automation, p.357-360, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123303]
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CITED BY 24

	Julian Culetu , Chaim Amir , John MacDonald, A practical repeater insertion method in high speed VLSI circuits, Proceedings of the 35th annual conference on Design automation, p.392-395, June 15-19, 1998, San Francisco, California, United States
	Charles Alpert , Anirudh Devgan, Wire segmenting for improved buffer insertion, Proceedings of the 34th annual conference on Design automation, p.588-593, June 09-13, 1997, Anaheim, California, United States
	Hai Zhou , D. F. Wong , I-Min Liu , Adnan Aziz, Simultaneous routing and buffer insertion with restrictions on buffer locations, Proceedings of the 36th ACM/IEEE conference on Design automation, p.96-99, June 21-25, 1999, New Orleans, Louisiana, United States
	T. Mitsuhashi , M. Murakata , K. Yoshida , T. Aoki, Physical design CAD in deep sub-micron era, Proceedings of the conference on European design automation, p.350-355, September 1996, Geneva, Switzerland
	Koichi Sato , Masamichi Kawarabayashi , Hideyuki Emura , Naotaka Maeda, Post-layout optimization for deep submicron design, Proceedings of the 33rd annual conference on Design automation, p.740-745, June 03-07, 1996, Las Vegas, Nevada, United States
	Maggie Kang , Wayne W.-M. Dai , Tom Dillinger , David LaPotin, Delay bounded buffered tree construction for timing driven floorplanning, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.707-712, November 09-13, 1997, San Jose, California, United States
	Hema Kapadia , Mark Horowitz, Using partitioning to help convergence in the standard-cell design automation methodology, Proceedings of the 36th ACM/IEEE conference on Design automation, p.592-597, June 21-25, 1999, New Orleans, Louisiana, United States
	Masako Murofushi , Takashi Ishioka , Masami Murakata , Takashi Mitsuhashi, Layout driven re-synthesis for low power consumption LSIs, Proceedings of the 34th annual conference on Design automation, p.666-669, June 09-13, 1997, Anaheim, California, United States
	Rajeev Murgai, Technology-based transformations, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Takumi Okamoto , Jason Cong, Buffered Steiner tree construction with wire sizing for interconnect layout optimization, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.44-49, November 10-14, 1996, San Jose, California, United States
	Guenter Stenz , Bernhard M. Riess , Bernhard Rohfleisch , Frank M. Johannes, Timing driven placement in interaction with netlist transformations, Proceedings of the 1997 international symposium on Physical design, p.36-41, April 14-16, 1997, Napa Valley, California, United States
	Luca P. Carloni , Kenneth L. McMillan , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.309-315, November 07-11, 1999, San Jose, California, United States
	Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France
	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
	Andrew B. Kahng , Stefanus Mantik, On mismatches between incremental optimizers and instance perturbations in physical design tools, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Rajeev Murgai, Layout-driven area-constrained timing optimization by net buffering, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Davide Pandini , Lawrence T. Pileggi , Andrzej J. Strojwas, Bounding the efforts on congestion optimization for physical synthesis, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Joe Gufeng Xi , Wayne Wei-Ming Dai, Useful-Skew Clock Routing with Gate Sizing for Low Power Design, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.163-179, June/July 1997
	Davide Pandini , Lawrence T. Pileggi , Andrzej J. Strojwas, Understanding and addressing the impact of wiring congestion during technology mapping, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Huan Ren , Shantanu Dutt, Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Deshanand P. Singh , Stephen D. Brown, An area-efficient timing closure technique for FPGAs using Shannon's expansion, Integration, the VLSI Journal, v.40 n.2, p.167-173, February, 2007
	Supratik Chakraborty , Rajeev Murgai, Layout-driven Timing Optimization by Generalized De Morgan Transform, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.647, January 07-11, 2002
	Stephen M. Plaza , Igor L. Markov , Valeria Bertacco, Optimizing non-monotonic interconnect using functional simulation and logic restructuring, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA
	Kai-hui Chang , Igor L. Markov , Valeria Bertacco, SafeResynth: A new technique for physical synthesis, Integration, the VLSI Journal, v.41 n.4, p.544-556, July, 2008