Performance-driven simultaneous place and route for row-based FPGAs

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Performance-driven simultaneous place and route for row-based FPGAs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 301 - 307

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Sudip K. Nag	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Rob A. Rutenbar	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 3

	R. Glenn Wood , Rob A. Rutenbar, FPGA routing and routability estimation via Boolean satisfiability, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.119-125, February 09-11, 1997, Monterey, California, United States
	Sudip K. Nag , Rob A. Rutenbar, Performance-driven simultaneous place and route for island-style FPGAs, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.332-338, November 05-09, 1995, San Jose, California, United States
	K. K. Lee , Martin D. F. Wong, LRoute: a delay minimal router for hierarchical CPLDs, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.12-20, February 2001, Monterey, California, United States