Circuit partitioning for huge logic emulation systems

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Circuit partitioning for huge logic emulation systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 244 - 249

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Nan-Chi Chou	Cadence Design Systems, 2655 Seely Rd. MS 6B1, San Jose, CA
Lung-Tien Liu	Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Chung-Kuan Cheng	Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Wei-Jin Dai	Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CA
Rodney Lindelof	Quickturn Design Systems, 440 Clyde Avenue, Mountain View, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 4, Citation Count: 20

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	5	Nan-Chi Chou, The application of hierarchical trees to circuit partitioning, clock net routing, and connectivity verification problems, University of California at San Diego, La Jolla, CA, 1993
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	11	J. Varghese, M. Butts, and J. Batcheller, "An Efficient Logic Emulation System," IEEE Trans. on VLSI, V. 1, N. 2, Jun. 1993, pp. 171 - 174.
	12	Y.-C. Wei and C.-K. Cheng, "Ratio Cut Partitioning for Hierarchical Designs," IEEE Trans. CAD, V. 10, N. 7, 1991, pp. 911 - 921.
	13	Nam Sung Woo , Jaeseok Kim, An efficient method of partitioning circuits for multiple-FPGA implementation., Proceedings of the 30th international conference on Design automation, p.202-207, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164669]
	14	Xilinx, Inc., The programmable Gate Array Data Book, Xilinx, San Jose, 1992.

CITED BY 20

	Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States
	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Performance-driven multi-FPGA partitioning using functional clustering and replication, Proceedings of the 35th annual conference on Design automation, p.283-286, June 15-19, 1998, San Francisco, California, United States
	Xiaoyu Song , William N. N. Hung , Alan Mishchenko , Malgorzata Chrzanowska-Jeske , Alan Coppola , Andrew Kennings, Board-level multiterminal net assignment, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Huiqun Liu , Kai Zhu , D. F. Wong, Circuit partitioning with complex resource constraints in FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.77-84, February 22-25, 1998, Monterey, California, United States
	Wai-Kei Mak , D. F. Wong, Board-level multi-terminal net routing for FPGA-based logic emulation, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.339-344, November 05-09, 1995, San Jose, California, United States
	Helena Krupnova , Ali Abbara , Gabrièle Saucier, A hierarchy-driven FPGA partitioning method, Proceedings of the 34th annual conference on Design automation, p.522-525, June 09-13, 1997, Anaheim, California, United States
	Wai-Kei Mak , D. F. Wong, Board-level multiterminal net routing for FPGA-based logic emulation, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.2, p.151-167, April 1997
	Roman Kužnar , Baldomir Zajc , Franc Brglez, A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions, Proceedings of the conference on European design automation, p.271-276, September 19-23, 1994, Grenoble, France
	Sverre Wichlund, On multilevel circuit partitioning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.505-511, November 08-12, 1998, San Jose, California, United States
	Wai-Kei Mak , D. F. Wong, On optimal board-level routing for FPGA-based logic emulation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.552-556, June 12-16, 1995, San Francisco, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Multi-way FPGA partitioning by fully exploiting design hierarchy, Proceedings of the 34th annual conference on Design automation, p.518-521, June 09-13, 1997, Anaheim, California, United States
	Huiqun Liu , D. F. Wong, Network flow based multi-way partitioning with area and pin constraints, Proceedings of the 1997 international symposium on Physical design, p.12-17, April 14-16, 1997, Napa Valley, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.638-643, November 10-14, 1996, San Jose, California, United States
	Wen-Jong Fang , Allen C.-H. Wu , Duan-Ping Chen, Module generation of complex macros for logic-emulation applications, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.69-75, February 09-11, 1997, Monterey, California, United States
	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Multiway FPGA partitioning by fully exploiting design hierarchy, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.34-50, Jan. 2000
	Xiaoyu Song , William N. N. Hung , Alan Mishchenko , Malgorzata Chrzanowska-Jeske , Andrew Kennings , Alan Coppola, Board-level multiterminal net assignment for the partial cross-bar architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.511-514, June 2003
	Wen-Jong Fang , Allen C. -H. Wu, Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs, IEEE Design & Test, v.15 n.2, p.65-72, April 1998
	Helena Krupnova , Gabriele Saucier, Iterative improvement based multi-way netlist partitioning for FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.117-es, January 1999, Munich, Germany