Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

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Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 238 - 243

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Roman Kužnar	Department of ECE, Tržaška 25, University of Ljubljana, 61000 Ljubljana, Slovenia
Franc Brglez	CBL, Dept. of Elec. & Computer Eng., North Carolina State University, Raleigh, N.C.
Baldomir Zajc	Department of ECE, Tržaška 25, University of Ljubljana, 61000 Ljubljana, Slovenia

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 17

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Roman Kužnar , Franc Brglez , Krzysztof Kozminski, Cost minimization of partitions into multiple devices, Proceedings of the 30th international conference on Design automation, p.315-320, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164910]
	4	Nam Sung Woo , Jaeseok Kim, An efficient method of partitioning circuits for multiple-FPGA implementation., Proceedings of the 30th international conference on Design automation, p.202-207, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164669]
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	14	James Hwang , Abbas El Gamal, Optimal replication for min-cut partitioning, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.432-435, November 1992, Santa Clara, California, United States
	15	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	16	R. Kuznar, F. Brglez, and B. Zajc. A Unified Cost Model for K-Way Netlist Partitioning with Replication. Technical report, CBL (CAD Benchmarking Laboratory), Elec. & Comp. Engineering, NCSU, Raleigh, N.C., 1994.
	17	Lars Hagen , Andrew B. Kahng, A new approach to effective circuit clustering, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.422-427, November 1992, Santa Clara, California, United States

CITED BY 17

	Helena Krupnova , Ali Abbara , Gabrièle Saucier, A hierarchy-driven FPGA partitioning method, Proceedings of the 34th annual conference on Design automation, p.522-525, June 09-13, 1997, Anaheim, California, United States
	Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States
	David Ihsin Cheng , Chih-Chang Lin , Malgorzata Marek-Sadowska, Circuit partitioning with logic perturbation, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.650-655, November 05-09, 1995, San Jose, California, United States
	Yu-Liang Wu , Xiao-Long Yuan , David Ihsin Cheng, Circuit partitioning with coupled logic restructuring techniques, Proceedings of the 2000 conference on Asia South Pacific design automation, p.655-660, January 2000, Yokohama, Japan
	Roman Kužnar , Baldomir Zajc , Franc Brglez, A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions, Proceedings of the conference on European design automation, p.271-276, September 19-23, 1994, Grenoble, France
	Morgan Enos , Scott Hauck , Majid Sarrafzadeh, Replication for logic bipartitioning, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.342-349, November 09-13, 1997, San Jose, California, United States
	Wen-Jong Fang , Allen C.-H. Wu, Performance-driven multi-FPGA partitioning using functional clustering and replication, Proceedings of the 35th annual conference on Design automation, p.283-286, June 15-19, 1998, San Francisco, California, United States
	Wai-Kei Mak, Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead, Proceedings of the 2001 international symposium on Physical design, p.100-105, April 01-04, 2001, Sonoma, California, United States
	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Sverre Wichlund, On multilevel circuit partitioning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.505-511, November 08-12, 1998, San Jose, California, United States
	Prashant Sawkar , Donald Thomas, Multi-way partitioning for minimum delay for look-up table based FPGAs, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.201-210, June 12-16, 1995, San Francisco, California, United States
	Dirk Behrens , Klaus Harbich , Erich Barke, Hierarchical partitioning, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.470-477, November 10-14, 1996, San Jose, California, United States
	Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001
	Wen-Jong Fang , Allen C.-H. Wu, Multiway FPGA partitioning by fully exploiting design hierarchy, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.1, p.34-50, Jan. 2000
	Wen-Jong Fang , Allen C.-H. Wu, A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.638-643, November 10-14, 1996, San Jose, California, United States
	Yu-Liang Wu , Chak-Chung Cheung , David Ihsin Cheng , Hongbing Fan, Further improve circuit partitioning using GBAW logic perturbation techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.451-460, June 2003
	Helena Krupnova , Gabriele Saucier, Iterative improvement based multi-way netlist partitioning for FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.117-es, January 1999, Munich, Germany