Error diagnosis for transistor-level verification

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Error diagnosis for transistor-level verification

Full text

Pdf (267 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 218 - 224

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Andreas Kuehlmann	IBM Thomas J. Watson Research Center, Yorktown Heights, N.Y.
David I. Cheng	Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, C.A.
Arvind Srinivasan	IBM Thomas J. Watson Research Center, Yorktown Heights, N.Y.
David P. LaPotin	IBM Thomas J. Watson Research Center, Yorktown Heights, N.Y.

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/196244.196358 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	2	M. S. Abadir, J. Ferguson, and T. E. Kirkland, "Logic design verification via test generation," IEEE Transactions on Computer-Aided Design, vol. 7, pp. 138- 148, January 1988.
	3	J. Jain, J. Bitner, D. S. Fussel, and J. A. Abraham, "Probabilistic design verification," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 468-471, IEEE, November 1991.
	4	J. C. Madre, O. Coudert, and J. P. Billon, "Automating the diagnosis and the rectification of design errors with PRIAM," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 30-33, IEEE, November 1989.
	5	Pi-Yu Chung , Yi-Min Wang , Ibrahim N. Hajj, Diagnosis and correction of logic design errors in digital circuits, Proceedings of the 30th international conference on Design automation, p.503-508, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165003]
	6	H.-T. Liaw, J.-H. Tsaih, and C.-S. Lin, "Efficient automatic diagnosis of digital circuits," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 464-467, IEEE, November 1990.
	7	M. Tomita and H.-H. Jiang, "An algorithm for locating logic design errors," in Digest of Technical Papers of the IEEE International Conference on Computer- Aided Design, pp. 468-471, IEEE, November 1990.
	8	Irith Pomeranz , Sudhakar M. Reddy, On diagnosis and correction of design errors, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.500-507, November 07-11, 1993, Santa Clara, California, United States
	9	A. Kuehlmann, D. I. Cheng, A. Srinivasan, and D. P. LaPotin, "Error diagnosis for transistor-level verification," Tech. Rep. Computer Science, RC 19219 (~/:83668), IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598, October 1993.
	10	G. Ditlow, W. Donath, and A. Ruehli, "Logic equations for MOSFET circuits," in Proceedings of the IEEE International Symposium on Circuits and Systems, (Newport Beach, CA), pp. 752-755, IEEE, May 1983.
	11	R. E. Bryant, "Boolean analysis of MOS circuits," IEEE Transactions on Computer-Aided Design, vol. 6, pp. 634-649, July 1987.
	12	D. T. Blaauw , D. G. Saab , P. Banerjee , J. A. Abraham, Functional abstraction of logic gates for switch-level simulation, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	13	R. Rudell, "Dynamic variable ordering for ordered binary decision diagrams," in International Workshop on Logic Synthesis, (Tahoe City, CA), pp. 3a-1-3a- 12, May 1993.

CITED BY 13

	Shi-Yu Huang, Towards the logic defect diagnosis for partial-scan designs, Proceedings of the 2001 conference on Asia South Pacific design automation, p.313-318, January 2001, Yokohama, Japan
	Vamsi Boppana , Rajarshi Mukherjee , Jawahar Jain , Masahiro Fujita , Pradeep Bollineni, Multiple error diagnosis based on xlists, Proceedings of the 36th ACM/IEEE conference on Design automation, p.660-665, June 21-25, 1999, New Orleans, Louisiana, United States
	Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Juin-Yeu Joseph Lu, Fault-simulation based design error diagnosis for sequential circuits, Proceedings of the 35th annual conference on Design automation, p.632-637, June 15-19, 1998, San Francisco, California, United States
	A. Wahba , D. Borrione, Automatic diagnosis may replace simulation for correcting simple design errors, Proceedings of the conference on European design automation, p.476-481, September 1996, Geneva, Switzerland
	Shi-Yu Huang , Kuang-Chien Chen , Kwang-Ting Cheng, Error correction based on verification techniques, Proceedings of the 33rd annual conference on Design automation, p.258-261, June 03-07, 1996, Las Vegas, Nevada, United States
	Alireza Ejlali , Ejlali Ghassem Miremadi, Switch-level emulation, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Shi-Yu Huang, A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis, Journal of Electronic Testing: Theory and Applications, v.19 n.2, p.161-172, April 2003
	Wei Huang , PuShan Tang , Min Ding, Sequential equivalence checking using cuts, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yu-Chiun Lin , Shi-Yu Huang, Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults, Journal of Electronic Testing: Theory and Applications, v.22 n.2, p.151-159, April 2006
	Görschwin Fey , Sean Safarpour , Andreas Veneris , Rolf Drechsler, On the relation between simulation-based and SAT-based diagnosis, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Alireza Ejlali , Seyed Ghassem Miremadi, Emulating switch-level models of CMOS circuits, Microelectronic Engineering, v.84 n.2, p.204-212, February, 2007
	John Moondanos, From Error to Error: Logic Debugging in the Many-Core Era, Electronic Notes in Theoretical Computer Science (ENTCS), v.174 n.4, p.3-7, May, 2007
	Alper Sen, Error Diagnosis in Equivalence Checking of High Performance Microprocessors, Electronic Notes in Theoretical Computer Science (ENTCS), v.174 n.4, p.9-18, May, 2007