Microarchitectural synthesis of VLSI designs with high test concurrency

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Microarchitectural synthesis of VLSI designs with high test concurrency

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 206 - 211

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Ian G. Harris	Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA
Alex Orailoglu	Department of Computer Science and Engineering, University of California, San Diego, La Jolla, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 18

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Computer Science Press, 1990.
	2	P. H. Bardell, W. H. McAnney, and 3. Savir. Built-In Test for VLSL Wiley-Interscience, 1987.
	3	C.-H. Chen, C. Wu, and D. G. Saab. BETA: Behavioral Testability Analysis. Proceedings of the IEEE Conference on Computer Aided Design, pages 202-205, November 1991.
	4	Scott Chiu , Christos A. Papachristou, A design for testability scheme with applications to data path synthesis, Proceedings of the 28th conference on ACM/IEEE design automation, p.271-277, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127679]
	5	I. G. Harris and A. Orailo~lu. Effective Test Path Definition Assisted by High-Level Synthesis Modifications. Proceedings of the Synthesis and Simulation Meeting and International Exchange (SASIMI), pages 187-195, October 1993. Nara, Japan.
	6	I. G. Harris and A. Orailo~lu. Fine-Grained Concurrency in Test Scheduling for PartiM-Intrusion BIST. Proceedings of the European Design Automation Conference, pages 119-123, February 1994.
	7	R. Karri and A. Orailo~lu. Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs. In Proceedings of the 22nd International Symposium on Fault-Tolerant Computing, pages 519-526, July 1992.
	8	Ramesh Karri , Alex Orailoğlu, Area-efficient fault detection during self-recovering microarchitecture synthesis, Proceedings of the 31st annual conference on Design automation, p.552-556, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196532]
	9	S. Y. Kung , Thomas Kailath , Harper J. Whitehouse, VLSI and Modern Signal Processing, Prentice Hall Professional Technical Reference, 1984
	10	Tien-Chien Lee , Wayne Wolf , Niraj K. Jha , John M. Acken, Behavioral Synthesis for Easy Testability in Data Path Allocation, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.29-32, October 11-14, 1992
	11	E. J. McCluskey. Built-In Self-Test Techniques. IEEE Design and Test, pages 21-28, April 1985.
	12	Mujumdar, K. Saluja, and R Jain. Incorporating Testability Considerations in High-Level Synthesis. 22nd Fault Tolerant Computing Symposium, pages 272-279, July 1992.
	13	A. Orailo~lu and I. G. Harris. Test Path Generation and Test Scheduling for Self-Testable Designs. Proceedings of the IEEE Conference on Computer Design, pages 528- 531, October 1993.
	14	N. Park and A. C. Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Transactions on Computer Aided Design, 7(3):356- 370, March 1988.
	15	P. G. Paulin and 3. P. Knight. Force-Directed Scheduling for the Behavioral Synthesis of ASIC's. IEEE Transactions on Computer Aided Design, 8(6):661-679, June 1989.

CITED BY 18

	Kiarash Bazargan , Abhishek Ranjan , Majid Sarrafzadeh, Fast and accurate estimation of floorplans in logic/high-level synthesis, Proceedings of the 10th Great Lakes symposium on VLSI, p.95-100, March 02-04, 2000, Chicago, Illinois, United States
	Ramesh Karri , Alex Orailoğlu, Area-efficient fault detection during self-recovering microarchitecture synthesis, Proceedings of the 31st annual conference on Design automation, p.552-556, June 06-10, 1994, San Diego, California, United States
	M. Nourani , J. Carletta , C. Papachristou, A scheme for integrated controller-datapath fault testing, Proceedings of the 34th annual conference on Design automation, p.546-551, June 09-13, 1997, Anaheim, California, United States
	Alex Orailoglu , Ramesh Karri, Automatic Synthesis of Self-Recovering VLSI Systems, IEEE Transactions on Computers, v.45 n.2, p.131-142, February 1996
	I. Parulkar , S. K. Gupta , M. A. Breuer, Scheduling and module assignment for reducing BIST resources, Proceedings of the conference on Design, automation and test in Europe, p.66-73, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Sujit Dey , Vijay Gangaram , Miodrag Potkonjak, A controller-based design-for-testability technique for controller-data path circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.534-540, November 05-09, 1995, San Jose, California, United States
	Kenneth D. Wagner , Sujit Dey, High-level synthesis for testability: a survey and perspective, Proceedings of the 33rd annual conference on Design automation, p.131-136, June 03-07, 1996, Las Vegas, Nevada, United States
	Balakrishnan Iyer , Ramesh Karri, Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis, Proceedings of the 33rd annual conference on Design automation, p.137-142, June 03-07, 1996, Las Vegas, Nevada, United States
	M. F. Abdulla , C. P. Ravikumar , Anshul Kumar, Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems, Journal of Electronic Testing: Theory and Applications, v.12 n.3, p.199-216, June 1998
	Joan E. Carletta , Christos A. Papachristou, Behavioral Testability Insertion for Datapath/Controller Circuits, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.9-28, Aug. 1997
	M. L. Flottes , D. Hammad , B. Rouzeyre, Improving Testability of Non-Scan Designs during BehavioralSynthesis, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.29-42, Aug. 1997
	Mohammed Fadle Abdulla , C. P. Ravikumar , Anshul Kumar, Built-in Self Test Based on Multiple On-Chip Signature Checking, Journal of Electronic Testing: Theory and Applications, v.14 n.3, p.227-244, June 1999
	Sujit Dey , Anand Raghunathan , Kenneth D. Wagner, Design for Testability Techniques at the Behavioraland Register-Transfer Levels, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.79-91, Oct. 1998
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Allocation Techniques for Reducing BIST Area Overhead ofData Paths, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.149-166, Oct. 1998
	Christos A. Papachristou , Mikhail Baklashov , Kowen Lai, High-Level Test Synthesis for Behavioral and Structural Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.167-188, Oct. 1998
	M. Nourani , C. Papachristou, Structural BIST Insertion Using Behavioral Test Analysis, Proceedings of the 1997 European conference on Design and Test, p.64, March 17-20, 1997
	Subhrajit Bhattacharya , Sujit Dey , Bhaskar Sengupta, An RTL Methodology to Enable Low Overhead Combinational Testing, Proceedings of the 1997 European conference on Design and Test, p.146, March 17-20, 1997
	D. Berthelot , M. L. Flottes , B. Rouzeyre, A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis, Journal of Electronic Testing: Theory and Applications, v.17 n.3-4, p.331-339, June-August 2001