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Routing in a new 2-dimensional FPGA/FPIC routing architecture
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents
San Diego, California, United States
Pages: 171 - 176  
Year of Publication: 1994
ISBN:0-89791-653-0
Authors
Yachyang Sun  Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, Illinois
C. L. Liu  Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, Illinois
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 16,   Citation Count: 5
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Aptix Inc., FPIC AX1024D, Preliminary Data Sheet, August 1992.
 
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S. Brown, J. Rose, and Z. Vranesic, "A detailed router for field-programmable gate arrays," IEEE Transactions on Computer-Aided Design, vol. 11, no. 5, pp. 620-628, May 1992.
 
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A. E1 Gamal, J. Greene, J. Reyneri, E. Rogoyski, K. E1- Ayat, and A. Mohsen, "An architecture for electrically configurable gate arrays," IEEE Journal of Solid-State Circuits, vol. 24, no. 2, pp. 394-398, April 1989.
 
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R. Guo, H. Nguyen, A. Srinivasan, H. Verheyen, H. Cai, S. Law, and A. Mohsen, "A 1024 pin universal interconnect array with routing architecture," IEEE Custom Integrated Circuits Conference, 1992, pp. 4.5.1-4.5.4.
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Y. Sun and C. L. Liu, manuscript, February 1994.
 
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Xilinx Inc., XC~O00 Logic Cell Array Family, Technical Data, 1990.