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Minimization of memory traffic in high-level synthesis
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents
San Diego, California, United States
Pages: 149 - 154  
Year of Publication: 1994
ISBN:0-89791-653-0
Authors
David J. Kolson  Department of Information and Computer Science, University of California, Irvine, Irvine, CA
Alexandru Nicolau  Department of Information and Computer Science, University of California, Irvine, Irvine, CA
Nikil Dutt  Department of Information and Computer Science, University of California, Irvine, Irvine, CA
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 5,   Citation Count: 7
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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D. Callahan, J. Cocke, and K. Kennedy. Estimating Interlock and Improving Balance for Pipelined Architectures. Proceedings of ICPP, 1987.
 
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R. Camposano. Path-Based Scheduling for Synthesis. IEEE Trans. on CAD, 10(1), 1991.
 
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C. Chu, M. Potkonjak, M. Thaler, and J. Rabey. HYPER: An Interactive Synthesis Environment for High Performance Real Time Applications. ICCD-89, 1989.
 
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F. Franssen, M. van Swaaij, F. Catthoor, and H. De Man. Modeling Piece-wise Linear and Data dependent Signal Indexing for Multi-dimensional Signal Processing. 6th International Workshop on High-Level Synthesis, November 1992.
 
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D. J. Kolson, A. Nicolau, and N. Dutt. Minimization of Memory Traffic in High-Level Synthesis. Technical Report 93-46, U.C. Irvine, October 1993.
 
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K. O'Brien, M. Rahmouni, and A. Jerraya. DLS: A Scheduling Algorithm for High-Level Synthesis in VHDL. EDAC-93, 1993.
 
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C. Park, T. Kim, and C. L. Liu. Register Allocation for Data Flow Graphs with Conditional Branches and Loops. Euro- DAC '93, 1993.
 
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N. Park and A. C. Parker. Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Trans. on CAD, 7(3), 1988.
 
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P. Pgchmiiller, M. Glesner, and F. Longsen. High-Level Synthesis Transformations for Programmable Architectures. Euro- DAC '93, 1993.
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L. Ramachandran, D. D. Gajski, and V. Chaiyakul. An Algorithm for Array Variable Clustering. EDAC-9$, 1994.
 
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C. B. Shung et al. An Integrated CAD System for Algorithm- Specific IC Design. IEEE Trans. on CAD, April 1991.
 
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CITED BY  7

Collaborative Colleagues:
David J. Kolson: colleagues
Alexandru Nicolau: colleagues
Nikil Dutt: colleagues