Statistical delay modeling in logic design and synthesis

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Statistical delay modeling in logic design and synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 126 - 130

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Horng-Fei Jyu	Department of Electrical Engineering, Princeton University, Princeton, NJ
Sharad Malik	Department of Electrical Engineering, Princeton University, Princeton, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 6

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Jacques Benkoski, Statistical timing verification and delay fault detection by formal signal interaction modeling in a multi-level timing simulator, 1989
	2	Stephen W. Director, Peter Feldmann, and Kannan Krishna. Optimization of Parametric Yield: A Tutorial. International Journal of High Speed Electronics, 3(1), 1992.
	3	Stephen W. Director, Peter Feldmann, and Kannan Krishna. Statistical integrated circuit design. IEEE Transactions on Solid-State Circuits, 28(3), March 1993.
	4	Andreas G. Andreou et al. Current mode subthreshold mos circuits for analog VLSI neural systems. IEEE Transactions on Neural Networks, 2(2):205-213, March 1991.
	5	Horng-Fei Jyu and Sharad Malik. Statistical Timing Optimization of Combinational Logic Circuits. In Proceedings of the International Conference on Computer Design, October 1993.
	6	Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, and Kurt Keutzer. Statistical Timing Analysis of Combinational Logic Circuits. IEEE Transactions on VLSI Systems, 1(2), June 1993.
	7	Christopher Michael , Mohammed I. Ismail, Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits, Kluwer Academic Publishers, Norwell, MA, 1993
	8	Raymond H. Myers. Classical and Modern Regression with Application. PWS-KENT publishing Company, 1990.
	9	Andrzej J. Strojwas, Statistical Design of Integrated Circuits, IEEE Press, Piscataway, NJ, 1987
	10	Ping Yang, Dale E. Hocevar, Paul F. Cox, Charles Machala, and Pallab K. Chatterjee. An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design. IEEE Transactions on Computeraided design, CAD-5(1), Jan. 1986.

CITED BY 6

	Jing-Jia Liou , Angela Krstic , Kwang-Ting Cheng , Deb Aditya Mukherjee , Sandip Kundu, Performance sensitivity analysis using statistical method and its applications to delay, Proceedings of the 2000 conference on Asia South Pacific design automation, p.587-592, January 2000, Yokohama, Japan
	Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States
	Yi-Min Jiang , Kwang-Ting Cheng, Analysis of performance impact caused by power supply noise in deep submicron devices, Proceedings of the 36th ACM/IEEE conference on Design automation, p.760-765, June 21-25, 1999, New Orleans, Louisiana, United States
	Hiroyuki Tomiyama , Akihiko Inoue, Statistical performance-driven module binding in high-level synthesis, Proceedings of the 11th international symposium on System synthesis, p.66-71, December 02-04, 1998, Hsinchu, Taiwan, China
	Azadeh Davoodi , Ankur Srivastava, Voltage scheduling under unpredictabilities: a risk management paradigm, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.354-368, April 2005
	Kanupriya Gulati , Sunil P. Khatri, Accelerating statistical static timing analysis using graphics processing units, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan