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The minimization and decomposition of interface state machines
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents
San Diego, California, United States
Pages: 120 - 125  
Year of Publication: 1994
ISBN:0-89791-653-0
Authors
Ajay J. Daga  ECES Department, The University of Michigan, Ann Arbor, MI
William P. Birmingham  ECES Department, The University of Michigan, Ann Arbor, MI
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 8,   Citation Count: 1
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Sakallah, K.A., T.N. Mudge, and O.A. Olukotun. Timing Verification and Optimal Clocking of Synchronous Digital Circuits. In Proceedings of the International Conference on Computer-Aided Design. IEEE, November 1990.
2
N. Weiner , A. Sangiovanni-Vincentelli, Timing analysis in a logic synthesis environment, Proceedings of the 26th ACM/IEEE conference on Design automation, p.655-661, June 25-28, 1989, Las Vegas, Nevada, United States  [doi>10.1145/74382.74498]
 
3
Patrick C. McGeer , Robert K. Brayton, Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications, Kluwer Academic Publishers, Norwell, MA, 1991
 
4
Gupta, A.P. Symbolic Timing Verification for Sequential Path Tracing. Technical Report, Carnegie Mellon University, November 1992.
 
5
Daga, A.J. and W.P. Birmingham. VITCh: A Methodology for the Timing Verification of Board-Level Circuits. In TAU'93, ACM, September 1993.
 
6
Zvi Kohavi , Richard W. Hamming , Edward A. Feigenbaum, Switching and Finite Automata Theory: Computer Science Series, McGraw-Hill Higher Education, 1990
 
7
Microprocessors Handbook. 1990, lntel Corporation.
 
8
Gaetano Borriello, A New Interface Specification Methodology and, University of California at Berkeley, Berkeley, CA, 1988

CITED BY
Ajay J. Daga , Peter R. Suaris, Interface timing verification drives system design, Proceedings of the 34th annual conference on Design automation, p.240-245, June 09-13, 1997, Anaheim, California, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Verification


General Terms:
Algorithms, Design, Theory, Verification

Collaborative Colleagues:
Ajay J. Daga: colleagues
William P. Birmingham: colleagues

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