Automated multi-cycle symbolic timing verification of microprocessor-based designs

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Automated multi-cycle symbolic timing verification of microprocessor-based designs

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 113 - 119

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Anurag P. Gupta	ECE Department, Carnegie Mellon University, Pittsburgh, PA
Daniel P. Siewiorek	ECE Department, Carnegie Mellon University, Pittsburgh, PA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 12, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. Amon , G. Borriello, An approach to symbolic timing verification, Proceedings of the 29th ACM/IEEE conference on Design automation, p.410-413, June 08-12, 1992, Anaheim, California, United States
	2	Pranav Ashar , Sujit Dey , Sharad Malik, Exploiting multi-cycle false paths in the performance optimization of sequential circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.510-517, November 1992, Santa Clara, California, United States
	3	J. Benkoski, E. V. Meersch, L. Claesen, and H. De Man. Efficient algorithms for solving the false path problem in timing verification. ICCAD, pages 44-47. 1987.
	4	J. Benkoski and A. J. Strojwas. A new approach to hierarchical and statistical timing simulation. IEEE Trans. on CAD, CAD-6(6):1039- 1052, Nov. 1987.
	5	Cadence Design Systems. Veritime Reference Manual, 1989.
	6	H.C. Chen and D. H. C. Du. Path sensitization in critical path problem. ICCAD, pages 208-211.1991.
	7	S. Devadas, K. Keutzer, and S. Malik. Delay computation in combinational logic circuits: Theory and algorithms. ICCAD, pages 176-179. 1991.
	8	Dimitris Doukas , Andrea S. LaPaugh, CLOVER: a timing constraints verification system, Proceedings of the 28th conference on ACM/IEEE design automation, p.662-667, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127747]
	9	Anurag Prakash Gupta, Timing verification of microprocessor-based designs, Carnegie Mellon University, Pittsburgh, PA, 1994
	10	R. B. Hitchcock, Timing verification and the timing analysis program, Papers on Twenty-five years of electronic design automation, p.446-456, June 1988 [doi>10.1145/62882.62936]
	11	Alexander T. Ishii , Charles E. Leiserson, A timing analysis of level-clocked circuitry, Proceedings of the sixth MIT conference on Advanced research in VLSI, p.113-130, March 1990, Boston, Massachusetts, United States
	12	Masamichi Kawarabayashi , Narendra Shenoy , Alberto Sangiovanni-Vincentelli, A verification technique for gated clock, Proceedings of the 30th international conference on Design automation, p.123-127, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164624]
	13	Alan R. Martello , Steven P. Levitan , Donald M. Chiarulli, Timing verification using HDTV, Proceedings of the 27th ACM/IEEE conference on Design automation, p.118-123, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123238]
	14	A Miczo, Digital logic testing and simulation, Harper & Row Publishers, Inc., New York, NY, 1985
	15	Karem A. Sakallah , Trevor N. Mudge , Oyekunle A. Olukotun, Analysis and design of latch-controlled synchronous digital circuits, Proceedings of the 27th ACM/IEEE conference on Design automation, p.111-117, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123237]
	16	Stephen Wolfram, Mathematica: a system for doing mathematics by computer (2nd ed.), Addison Wesley Longman Publishing Co., Inc., Redwood City, CA, 1991

CITED BY 7

	Kazuhiro Nakamura , Kazuyoshi Takagi , Shinji Kimura , Katsumasa Watanabe, Waiting false path analysis of sequential logic circuits for performance optimization, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.392-395, November 08-12, 1998, San Jose, California, United States
	Kazuhiro Nakamura , Shinji Maruoka , Shinji Kimura , Katsumasa Watanabe, Multi-clock path analysis using propositional satisfiability, Proceedings of the 2000 conference on Asia South Pacific design automation, p.81-86, January 2000, Yokohama, Japan
	Hiroyuki Higuchi, An implication-based method to detect multi-cycle paths in large sequential circuits, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Kai Yang , Kwang-Ting Cheng, Efficient identification of multi-cycle false path, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Hiroyuki Higuchi , Yusuke Matsunaga, Enhancing the performance of multi-cycle path analysis in an industrial setting, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.192-198, January 27-30, 2004, Yokohama, Japan
	Ki-Seok Chung , Rajesh K. Gupta , Taewhan Kim , C. L. Liu, Synthesis and Optimization of Combinational Interface Circuits, Journal of VLSI Signal Processing Systems, v.31 n.3, p.243-261, July 2002
	Lei Cheng , Deming Chen , Martin D. F. Wong , Mike Hutton , Jason Govig, Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California