ACM Portal
  Subscribe (Full Service)    Register (Limited Service, Free)    Login
  Search:   The ACM Digital Library   The Guide
  
ACM Home Page
Please provide us with feedback. Feedback
Clock grouping: a low cost DFT methodology for delay testing
Full text PdfPdf (440 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents
San Diego, California, United States
Pages: 94 - 99  
Year of Publication: 1994
ISBN:0-89791-653-0
Authors
Wen-Chang Fang  Electrical Engineering Systems, University of Southern California, Los Angeles CA
Sandeep K. Gupta  Electrical Engineering Systems, University of Southern California, Los Angeles CA
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Citation Count: 1
Additional Information:

references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/196244.196291
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
Tapan J. Chakraborty , Vishwani D. Agrawal , Michael L. Bushnell, Design for testability for path delay faults in sequential circuits, Proceedings of the 30th international conference on Design automation, p.453-457, June 14-18, 1993, Dallas, Texas, United States  [doi>10.1145/157485.164973]
 
2
Kwang-Ting Cheng , Srinivas Devadas , Kurt Keutzer, A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.403-410, October 26-30, 1991
 
3
Bulent I. Dervisoglu , Gayvin E. Stong, Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.365-374, October 26-30, 1991
 
4
K. L. Einspahr, S. G. Seth, and V. D. Agrawal. Clock Partitioning for Testability. In Proceedings of Third Great Lakes Symposium on VLSI, pages 42-46, 1993.
 
5
W.-C. Fang and S. K. Gupta. Clock Grouping: A Low Cost DFT Methodology for Delay Testing. Technical Report 94-04, University of Southern California, 1994.
 
6
J. C. Lin and S. Reddy. On Delay Fault Testing in Logic Circuits. IEEE Trans, on CAD, 6(5):694-703, September 1987.
 
7
Y. K. Malaiya. Testing for Timing Faults in Synchronous Sequential Integrated Circuits. In Proceedings IEEE International Test Conference, pages 560-571, 1983.
 
8
W. Mao and M. D. Ciletti. Arrangement of Latches in Scan-path Design to Improve Delay Fault Coverage. In Proceedings IEEE International Test Conference, pages 387-393, 1990.
9
Weiwei Mao , Michael D. Ciletti, Correlation-reduced scan-path design to improve delay fault coverage, Proceedings of the 28th conference on ACM/IEEE design automation, p.73-79, June 17-22, 1991, San Francisco, California, United States  [doi>10.1145/127601.127631]
 
10
Bejoy G. Oomman , Prasad Kongara , Chittaranjan Mallipeddi, Amdahl Corporation Board Delay Test System, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.558-567, September 20-24, 1992
 
11
Srinivas Patil , Jacob Savir, Skewed-Load Transition Test: Part 2, Coverage, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.714-722, September 20-24, 1992
 
12
Jacob Savir, Skewed-Load Transition Test: Part 1, Calculus, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.705-713, September 20-24, 1992
 
13
Jacob Savir , Robert F. Berry, At-Speed Test is not Necessarily an AC Test, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.722-728, October 26-30, 1991
 
14
G. L. Smith. Model for Delay Faults Based on Paths. In Proceedings IEEE International Test Conference, pages 342-349, 1985.

CITED BY
Miron Abramovici , Xiaoming Yu , Elizabeth M. Rudnick, Low-cost sequential ATPG with clock-control DFT, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
  B.7 INTEGRATED CIRCUITS


General Terms:
Design, Experimentation, Performance, Verification

Collaborative Colleagues:
Wen-Chang Fang: colleagues
Sandeep K. Gupta: colleagues

The ACM Portal is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player