An exact algorithm for selecting partial scan flip-flops

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An exact algorithm for selecting partial scan flip-flops

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 81 - 86

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Srimat T. Chakradhar	C & C Research Laboratories, NEC USA, 4 Independence Way, Princeton, NJ
Arun Balakrishnan	RUTCOR, PO Box 5062, Rutgers University, New Brunswick, NJ
Vishwani D. Agrawal	AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 24

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Miron Abramovici , James J. Kulikowski , Rabindra K. Roy, The Best Flip-Flops to Scan, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.166-173, October 26-30, 1991
	3	Vishiwani D. Agrawal , Kwang-Ting Cheng , Daniel D. Johnson , Tony Sheng Lin, Designing Circuits with Partial Scan, IEEE Design & Test, v.5 n.2, p.8-15, March 1988 [doi>10.1109/54.2032]
	4	H.-K. T. Ma, S. Devadas, A. R. Newton, and A. Sangiovanni- Vincentelli, "An Incomplete Scan Design Approach to Test Generation for Sequential Machines," in Proc. of the Intl. Test Conf., pp. 730 - 734, 1988.
	5	V. Chickermane and J. H. Patel, "A Fault Oriented Partial Scan Design Approach," in Proc. of the Intl. Conf. on Computer-Aided Design, pp. 400 - 403, November 1991.
	6	Prashant S. Parikh , Miron Abramovici, A cost-based approach to partial scan, Proceedings of the 30th international conference on Design automation, p.255-259, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164882]
	7	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
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	9	D. Lee and S. Reddy, "On Determining Scan Flip-Flops in Partial- Scan Designs," in Proc. of the Intl. Conf. on Computer-Aided Design, pp. 322 - 325, November 1990.
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	12	Sungju Park , Sheldon B. Akers, A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.303-311, September 20-24, 1992
	13	S. E. Tai and D. Bhattacharya, "A Three Stage Partial Scan Design Method using the Sequential Circuit Flow Graph," in Proc. of the 7th Intl. Conf. on VLSI Design, pp. 101-106, January 1994.
	14	Pranav Ashar , Sharad Malik, Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications, Proceedings of the 31st annual conference on Design automation, p.77-80, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196283]
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	18	Srimat T. Chakradhar , Sujit Dey, Resynthesis and retiming for optimum partial scan, Proceedings of the 31st annual conference on Design automation, p.87-93, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196288]

CITED BY 24

	Chih-Chang Lin , Mike Tien-Chien Lee , Malgorzata Marek-Sadowska , Kuang-Chien Chen, Cost-free scan: a low-overhead scan path design methodology, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.528-533, November 05-09, 1995, San Jose, California, United States
	Pranav Ashar , Sharad Malik, Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications, Proceedings of the 31st annual conference on Design automation, p.77-80, June 06-10, 1994, San Diego, California, United States
	Dong Xiang , Srikanth Venkataraman , W. Kent Fuchs , Janak H. Patel, Partial scan design based on circuit state information, Proceedings of the 33rd annual conference on Design automation, p.807-812, June 03-07, 1996, Las Vegas, Nevada, United States
	Srimat T. Chakradhar , Sujit Dey, Resynthesis and retiming for optimum partial scan, Proceedings of the 31st annual conference on Design automation, p.87-93, June 06-10, 1994, San Diego, California, United States
	Toshinori Hosokawa , Masayoshi Yoshimura , Mitsuyasu Ohta, Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times, Proceedings of the 2001 conference on Asia South Pacific design automation, p.485-491, January 2001, Yokohama, Japan
	Peichen Pan , C. L. Liu, Partial scan with pre-selected scan signals, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.189-194, June 12-16, 1995, San Francisco, California, United States
	Priyadarshan Patra , Unni Narayanan, Automated phase assignment for the synthesis of low power domino circuits, Proceedings of the 36th ACM/IEEE conference on Design automation, p.379-384, June 21-25, 1999, New Orleans, Louisiana, United States
	Qiushuang Zhang , Ian Harris, Partial BIST insertion to eliminate data correlation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.395-399, November 07-11, 1999, San Jose, California, United States
	Toshinobu Ono, Selecting partial scan flip-flops for circuit partitioning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.646-650, November 06-10, 1994, San Jose, California, United States
	Albrecht P. Stroele , Hans-Joachim Wunderlich, Test register insertion with minimum hardware cost, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.95-101, November 05-09, 1995, San Jose, California, United States
	Krishnendu Chakrabarty, A synthesis-for-transparency approach for hierarchical and system-on-a-chip test, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.167-179, April 2003
	Peter Dahlgren, Oscillation control in logic simulation using dynamic dominance graphs, Proceedings of the 33rd annual conference on Design automation, p.155-160, June 03-07, 1996, Las Vegas, Nevada, United States
	Debesh Kumar Das , Satoshi Ohtake , Hideo Fujiwara, New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency, Journal of Electronic Testing: Theory and Applications, v.20 n.3, p.315-323, June 2004
	Dong Xiang , Janak H. Patel, Partial Scan Design Based on Circuit State Information and Functional Analysis, IEEE Transactions on Computers, v.53 n.3, p.276-287, March 2004
	Peichen Pan , C. L. Liu, Partial Scan with Preselected Scan Signals, IEEE Transactions on Computers, v.48 n.9, p.1000-1005, September 1999
	Sandhya Seshadri , Michael S. Hsiao, Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.131-145, Feb/April 2000
	Tianruo Yang , Zebo Peng, Incremental Testability Analysis for Partial Scan Selection and Design Transformations, Journal of Electronic Testing: Theory and Applications, v.14 n.1-2, p.103-113, Feb./April 1999
	Xijiang Lin , Irith Pomeranz , Sudhakar M. Reddy, Full scan fault coverage with partial scan, Proceedings of the conference on Design, automation and test in Europe, p.97-es, January 1999, Munich, Germany
	Gundolf Kiefer , Hans-Joachim Wunderlich, Deterministic BIST with Partial Scan, Journal of Electronic Testing: Theory and Applications, v.16 n.3, p.169-177, June 2000
	P. Walker , S. Ghosh, Exploiting temporal independence in distributed preemptive circuit simulation, Proceedings of the 1997 European conference on Design and Test, p.378, March 17-20, 1997
	Zhihong Zeng , Qiushuang Zhang , Ian Harris , Maciej Ciesielski, Fast Computation of Data Correlation Using BDDs, Proceedings of the conference on Design, Automation and Test in Europe, p.10122, March 03-07, 2003
	Sandhya Seshadri , Michael S. Hsiao, Behavioral-Level DFT via Formal Operator Testability Measures, Journal of Electronic Testing: Theory and Applications, v.18 n.6, p.595-611, December 2002
	Bruce S. Greene , Samiha Mourad, Partial Scan Testing on the Register-Transfer Level, Journal of Electronic Testing: Theory and Applications, v.18 n.6, p.613-626, December 2002
	Chin-Lung Chuang , Wei-Hsiang Cheng , Dong-Jung Lu , Chien-Nan Jimmy Liu, Hybrid Approach to Faster Functional Verification with Full Visibility, IEEE Design & Test, v.24 n.2, p.154-162, March 2007