Performance analysis based on timing simulation

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Performance analysis based on timing simulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 70 - 76

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Christian D. Nielsen	Department of Computer Science, Technical University of Denmark, Building 344, Lyngby, DK
Michael Kishinevsky	Department of Computer Science, Technical University of Denmark, Building 344, Lyngby, DK

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 20, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Baccelli, G.Cohen, G.J.Olsder, and J.E Quadrat. Synchronization and Linearity. John Wiley and Sons, 1992.
	2	Steven Morgan Burns, Performance analysis and optimization of asynchronous circuits, California Institute of Technology, Pasadena, CA, 1992
	3	C.D.Nielsen and M.Kishinevsky. Performance analysis based on timing simulation. ID-TR: 1993-125, Technical University of Denmark, Nov. 1993 (ftp ftp.id.dth.dk, pub/TR/1993/ID- TR: 1993-125.ps.Z).
	4	T.-A. Chu. Synthesis of Self-timed VLSI Circuits from Graphtheoretic Specifications. PhD thesis, MIT, June 1987.
	5	F. Commoner, A.W. Holt, S.Even, and A.Pnueli. Marked directed graphs. J. of Comp. and Syst. Sci., 5:511-523, 1971.
	6	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	7	J. Gunawardena. Timing analysis of digital circuits and the theory of rain-max functions. In Proc. of the ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 1993.
	8	M. Hartmann and J. Orlin. Finding minimum cost to time ratio cycles with small integral transit times. Networks, 23:567-574, August 1993.
	9	Michael Kishinevsky , Alex Kondratyev , Alexander Taubin , Victor Varshavsky , Alex Yakovlev , Eric Napelbaum , Olga Reva, Concurrent hardware: the theory and practice of self-timed design, John Wiley & Sons, Inc., New York, NY, 1994
	10	Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli, Algorithms for Synthesis and Testing of Asynchronous Circuits, Kluwer Academic Publishers, Norwell, MA, 1993
	11	E.L. Lawler. Combinatorial Optimization: Networks and Matroids. Holt, Rinehart and Winston, 1976.
	12	E Vanbekbergen, F. Catthoor, G. Goossens, and H. De Man. Optimized synthesis of asynchronous control circuits from graphtheoretic specifications. IEEE Tr. on Computer-Aided Design, pp. 1426-1438, Nov. 1992.
	13	N. Young, R. Tarjan, and J. Orlin. Faster parametric shortest path and minimum-balance algorithms. Networks, 21:205-221, 1991.

CITED BY 8

	O. Garnica , J. Lanchares , R. Hermida, Optimization of asynchronous delay-insensitive pipeline latency using stage reorganization and optimal stage parameter estimation, Fundamenta Informaticae, v.50 n.2, p.155-174, April 2002
	Daniel H. Linder , James C. Harden, Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry, IEEE Transactions on Computers, v.45 n.9, p.1031-1044, September 1996
	Ali Dasdan, Experimental analysis of the fastest optimum cycle ratio and mean algorithms, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.385-418, October 2004
	Girish Venkataramani , Seth C. Goldstein, Leveraging protocol knowledge in slack matching, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Girish Venkataramani , Seth C. Goldstein, Operation chaining asynchronous pipelined circuits, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Girish Venkataramani , Mihai Budiu , Tiberiu Chelcea , Seth C. Goldstein, Global critical path: a tool for system-level timing analysis, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Girish Venkataramani , Seth C. Goldstein, Slack analysis in the system design loop, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA
	Cristian Soviani , Ilija Hadžic , Stephen A. Edwards, Synthesis and optimization of pipelined packet processors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.2, p.231-244, February 2009