Synthesis of instruction sets for pipelined microprocessors

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Synthesis of instruction sets for pipelined microprocessors

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 5 - 11

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Ing-Jer Huang	Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
Alvin M. Despain	Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 22, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. M. Haney, "ISDS-A program that designs computer instruction sets," Fall Joint Computer Conference, 1969
	2	Pradip Bose , Edward S. Davidson, Design of instruction set architectures for support of high-level languages, Proceedings of the 11th annual international symposium on Computer architecture, p.198-206, January 1984
	3	J. E Bennett, A Methodology for Automated Design of Computer Instruction Sets, Ph.D. thesis, University of Cambridge, Computer Laboratory, 1988.
	4	Bruce Kester Holmer , David E. Culler , Alvin M. Despain, Automatic design of computer instruction sets, 1993
	5	Jun Sato , Masaharu Imai , Tetsuya Hakata , Alauddin Y. Alomary , Nobuyuki Hikichi, An Integrated Design Environment for Application Specific Integrated Processor, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.414-417, October 14-16, 1991
	6	Ing-Jer Huang, Bruce Holmer and Alvin Despain, "ASIA: Automatic Synthesis of Instruction-set Architectures," Proc. of SASIMI Workshop, Nara, Japan, Oct. 1993
	7	Ing-Jer Huang and Alvin Despain, "Synthesis of Application Specific Instruction Sets," submitted to Trans. on CAD, 1994
	8	Peter M. Kogge, The Architecture of Symbolic Computers, McGraw-Hill, Inc., New York, NY, 1990
	9	Srinivas Devadas and Richard Newton, "Algorithms for Hardware Allocation in Data Path Synthesis," IEEE Trans. on Computer-Aided Design, Vol. 8, No. 7, July 1989
	10	Gert Goossens, et al., "An Efficient Microcode Compiler for Application Specific DSP Processors," IEEE Trans. on Computer-Aided Design, Vol. 9, No. 9, September 1990
	11	Shi-Zheng Lin, Cheng-Tsung Hwang and Yu-Chin Hsu, "Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits," Proc. of ICCAD, 1991
	12	Ralph Haygood, A Prolog Benchmark Suite for Aquarius, University of California at Berkeley, Berkeley, CA, 1989
	13	Bill Bush, et al., The Berkeley Abstract Machine Instruction Manual, Internal Technical Report, Advanced Computer Architecture Laboratory, University of Southern California, 1990
	14	Bruce K. Holmer , Barton Sano , Michael Carlton , Peter Van Roy , Ralph Haygood , William R. Bush , Alvin M. Despain , Joan M. Pendleton , Tep Dobry, Fast Prolog with an extended general purpose architecture, Proceedings of the 17th annual international symposium on Computer Architecture, p.282-291, May 28-31, 1990, Seattle, Washington, United States

CITED BY 13

	Nguyen Ngoc Bình , Masaharu Imai , Akichika Shiomi , Nobuyuki Hikichi, A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts, Proceedings of the 33rd annual conference on Design automation, p.527-532, June 03-07, 1996, Las Vegas, Nevada, United States
	Michael Gschwind, Instruction set selection for ASIP design, Proceedings of the seventh international workshop on Hardware/software codesign, p.7-11, March 1999, Rome, Italy
	Yuichiro Miyaoka , Yoshiharu Kataoka , Nozomu Togawa , Massao Yanagisawa , Tatsuo Ohtsuki, Area/delay estimation for digital signal processor cores, Proceedings of the 2001 conference on Asia South Pacific design automation, p.156-161, January 2001, Yokohama, Japan
	Hoon Choi , Seung Ho Hwang , Chong-Min Kyung , In-Cheol Park, Synthesis of application specific instructions for embedded DSP software, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.665-671, November 08-12, 1998, San Jose, California, United States
	V. Salapura , M. Gschwind, Hardware/software co-design of a fuzzy RISC processor, Proceedings of the conference on Design, automation and test in Europe, p.875-882, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Ing-Jer Huang , Alvin M. Despain, Generating instruction sets and microarchitectures from applications, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.391-396, November 06-10, 1994, San Jose, California, United States
	M. Imai , N. Binh , A. Shiomi, A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs, Proceedings of the conference on European design automation, p.126-131, September 1996, Geneva, Switzerland
	Marnix Arnold , Henk Corporaal, Designing domain-specific processors, Proceedings of the ninth international symposium on Hardware/software codesign, p.61-66, April 2001, Copenhagen, Denmark
	Nozomu Togawa , Koichi Tachikake , Yuichiro Miyaoka , Masao Yanagisawa , Tatsuo Ohtsuki, Instruction set and functional unit synthesis for SIMD processor cores, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.743-750, January 27-30, 2004, Yokohama, Japan
	Hoon Choi , Jong-Sun Kim , Chi-Won Yoon , In-Cheol Park , Seung Ho Hwang , Chong-Min Kyung, Synthesis of Application Specific Instructions for Embedded DSP Software, IEEE Transactions on Computers, v.48 n.6, p.603-614, June 1999
	Naoki Tomono , Shunitsu Kohara , Jumpei Uchida , Yuichiro Miyaoka , Nozomu Togawa , Masao Yanagisawa , Tatsuo Ohtsuki, A processor core synthesis system in IP-based SoC design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Fei Sun , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha, Synthesis of custom processors based on extensible platforms, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.641-648, November 10-14, 2002, San Jose, California
	Koichi Tachikake , Nozomu Togawa , Yuichiro Miyaoka , Jinku Choi , Masao Yanagisawa , Tatsuo Ohtsuki, A hardware/software partitioning algorithm for SIMD processor cores, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan