Run-time generation of HPS microinstructions from a VAX instruction stream

ABSTRACT

The VAX architecture is a popular ISP architecture that has been implemented in several different technologies targeted to a wide range of performance specifications. However, it has been argued that the VAX has specific characteristics which preclude a very high performance implementation. We have developed a microarchitecture (HPS) which is specifically intended for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. In this paper, we concentrate on one particular aspect of an HPS implementation of the VAX architecture: the generation of HPS microinstructions (i.e. data flow nodes) from a VAX instruction stream.

REFERENCES

• 1: Anderson, D. W., Sparacio, F. J., Tomasulo, R. M., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling," IBM Journal of Research and Development, vol. 11, January, 1967, pp. 8-24.
• 2: Y. N. Patt , W. M. Hwu , M. Shebanow, HPS, a new microarchitecture: rationale and introduction, Proceedings of the 18th annual workshop on Microprogramming, p.103-108, December 03-06, 1985, Pacific Grove, California, United States
• 3: Y. N. Patt , S. W. Melvin , W. M. Hwu , M. C. Shebanow, Critical issues regarding HPS, a high performance microarchitecture, Proceedings of the 18th annual workshop on Microprogramming, p.109-116, December 03-06, 1985, Pacific Grove, California, United States
• 4: Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, January, 1967, pp. 25-33.
• 5: VAX Architecture Handbook, Digital Equipment Corporation, 1981.

INDEX TERMS

Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)

          Nouns: VAX

General Terms:
Design