The anatomy of the register file in a multiscalar processor

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The anatomy of the register file in a multiscalar processor

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International Symposium on Microarchitecture archive
Proceedings of the 27th annual international symposium on Microarchitecture table of contents

San Jose, California, United States

Pages: 181 - 190

Year of Publication: 1994

ISBN:0-89791-707-3

Authors

Scott E. Breach	Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI
T. N. Vijaykumar	Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI
Gurindar S. Sohi	Computer Sciences Department, University of Wisconsin-Madison, 1210 W. Dayton Street, Madison, WI

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 16, Citation Count: 16

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ABSTRACT

This paper presents the operation of the register file in the Multiscalar architecture. The register file provides the appearance of a logically centralized register file, yet is implemented as physically decentralized register files, queues, and control logic in a Multiscalar processor. We address the key issues of storage, communication, and synchronization required for successful design and discuss the complications that arise in the face of speculation. In particular, the hardware required to implement the register file is detailed, and software support to streamline the operation of the register file is described. Illustrative examples detailing important aspects of the operation of the register file and an evaluation of its effectiveness are provided.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 16

	Venkata Krishnan , Josep Torrellas, The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors, International Journal of Parallel Programming, v.29 n.1, p.3-33, February 2001
	Eric Rotenberg , Quinn Jacobson , Yiannakis Sazeides , Jim Smith, Trace processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.138-148, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	Chong-Liang Ooi , Seon Wook Kim , Il Park , Rudolf Eigenmann , Babak Falsafi , T. N. Vijaykumar, Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor, Proceedings of the 15th international conference on Supercomputing, p.368-380, June 2001, Sorrento, Italy
	Gurindar S. Sohi , Scott E. Breach , T. N. Vijaykumar, Multiscalar processors, ACM SIGARCH Computer Architecture News, v.23 n.2, p.414-425, May 1995
	Gurindar S. Sohi , Scott E. Breach , T. N. Vijaykumar, Multiscalar processors, 25 years of the international symposia on Computer architecture (selected papers), p.521-532, June 27-July 02, 1998, Barcelona, Spain
	Venkata Krishnan , Josep Torrellas, Hardware and software support for speculative execution of sequential binaries on a chip-multiprocessor, Proceedings of the 12th international conference on Supercomputing, p.85-92, July 1998, Melbourne, Australia
	T. N. Vijaykumar , Gurindar S. Sohi, Task selection for a multiscalar processor, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.81-92, November 1998, Dallas, Texas, United States
	Andreas Moshovos , Scott E. Breach , T. N. Vijaykumar , Gurindar S. Sohi, Dynamic speculation and synchronization of data dependences, ACM SIGARCH Computer Architecture News, v.25 n.2, p.181-193, May 1997
	Troy A. Johnson , Rudolf Eigenmann , T. N. Vijaykumar, Min-cut program decomposition for thread-level speculation, ACM SIGPLAN Notices, v.39 n.6, May 2004
	Chen-Yong Cher , T. N. Vijaykumar, Skipper: a microarchitecture for exploiting control-flow independence, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	J. Gregory Steffan , Christopher Colohan , Antonia Zhai , Todd C. Mowry, The STAMPede approach to thread-level speculation, ACM Transactions on Computer Systems (TOCS), v.23 n.3, p.253-300, August 2005
	Venkata Krishnan , Josep Torrellas, A Chip-Multiprocessor Architecture with Speculative Multithreading, IEEE Transactions on Computers, v.48 n.9, p.866-880, September 1999
	Troy A. Johnson , Rudolf Eigenmann , T. N. Vijaykumar, Speculative thread decomposition through empirical optimization, Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming, March 14-17, 2007, San Jose, California, USA
	Saisanthosh Balakrishnan , Gurindar S. Sohi, Exploiting Value Locality in Physical Register Files, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.265, December 03-05, 2003
	Paul Gratz , Karthikeyan Sankaralingam , Heather Hanson , Premkishore Shivakumar , Robert McDonald , Stephen W. Keckler , Doug Burger, Implementation and Evaluation of a Dynamically Routed Processor Operand Network, Proceedings of the First International Symposium on Networks-on-Chip, p.7-17, May 07-09, 2007
	Emre Ozer , Thomas M. Conte, High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm, IEEE Transactions on Parallel and Distributed Systems, v.16 n.12, p.1132-1142, December 2005