ACM Home Page
Please provide us with feedback. Feedback
Dynamic memory disambiguation for array references
Full text PdfPdf (924 KB)
Source International Symposium on Microarchitecture archive
Proceedings of the 27th annual international symposium on Microarchitecture table of contents
San Jose, California, United States
Pages: 105 - 111  
Year of Publication: 1994
ISBN:0-89791-707-3
Authors
David Bernstein  IBM Haifa Research Laboratory, Matam, Haifa 31905, Israel
Doron Cohen  IBM Haifa Research Laboratory, Matam, Haifa 31905, Israel
Dror E. Maydan  Silicon Graphics Corporation, Mountain View, CA and IBM Haifa Research Laboratory
Sponsors
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 18,   Citation Count: 8
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/192724.192737
What is a DOI?

ABSTRACT

Memory disambiguation, or alias analysis, is a key component of modern optimizing compilers. Any optimization that reorders or changes code containing memory operations must analyze the memory references to ensure that the original semantics of the program are not changed.The recent proliferation of machines able to exploit parallelism, either at the coarse grain or more commonly at the instruction level, has led to the development of sophisticated memory disambiguation algorithms. In particular, much work has been done on disambiguating array references across different loop iterations.While these algorithms can be very effective for certain classes of programs, there exists array references that cannot be disambiguated at compile time. Even references that theoretically can be disambiguated at compile time may require techniques that are much more sophisticated and expensive than currently used.In this paper, we present a new algorithm for dynamic memory disambiguation for array references that allows us to overcome limitations of static analysis. For array references that cannot be accurately analyzed at compile time, we defer the disambiguation process until run-time.We have implemented our analysis algorithm in a prototype version of the IBM XL compiler and used the generated information for several compiler optimizations: software pipelining with global instruction scheduling, loop-invariant motion and redundant load elimination. We evaluated the algorithm on an IBM POWER2 system using the SPEC92 benchmarks. We show that for numeric C benchmarks, dynamic memory disambiguation can greatly improve run-time performance. Perhaps more importantly, we show that even for the programs that cannot benefit from dynamic analysis, the overhead of our algorithm does not degrade performance.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
D. Bernstein and Y. Lavon. A software pipelining algorithm based on global instruction scheduling. Technical Report TR88.338, IBM Hails, Nov 1993.
4
 
5
M. Byler, M. Wolfe, J. Davies, C. Huson, and B. Leasure. Multiple version loops. In Proceedings of the International ConIerence on Parallel Processing, pages 312-318, 1987.
 
6
7
 
8
 
9
P. Feautrier. Parametric integer programming. Technical Report 209, Laboratoire Methodologie and Architecture Des Systemes Informatiques, Jan 1988.
10
 
11
L. Hendren and A. Nicolau. Parallelizing programs with recursive data structures. In international Conference on Parallel Processing, pages 49-56, August 1989.
12
 
13
KAP for IBM XL C User's Guide. Kuck & Associates, inc., 1993.
14
15
 
16
17
 
18
 
19
K. O'Brien, B. Itay, J. Minish, H. Schaffer, B. Schloss, A. Shepherd, and M. Zaleski. Advanced compiler technology for the RISC System/6000 architecture. In IBM RISC System/6000 Technology, pages 154-161. IBM SA23-2619, 1990.
20
 
21
 
22
 
23
New cpu benchmark suites from spec. In COMPCOM, 1992.
 
24
 
25
S. White, editor. IBM RiSG System/6000 Technology: Volume II. IBM, 1993.
 
26

CITED BY  8

Collaborative Colleagues:
David Bernstein: colleagues
Doron Cohen: colleagues
Dror E. Maydan: colleagues