FBRAM: a new form of memory optimized for 3D graphics

ABSTRACT

FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. The first is to convert the read-modify-write Z-buffer compare and RGB&agr; blend into a single write only operation. The second is to support two levels of rectangularly shaped pixel caches internal to the memory chip. The result is a 10 megabit part that, for 3D graphics, performs read-modify-write cycles ten times faster than conventional 60 ns VRAMs. A four-way interleaved 100MHz FBRAM frame buffer can Z-buffer up to 400 million pixels per second. Working FBRAM prototypes have been fabricated.

REFERENCES

• 1: Kurt Akeley , Tom Jermoluk, High-performance polygon rendering, Proceedings of the 15th annual conference on Computer graphics and interactive techniques, p.239-246, June 1988
• 2: Kurt Akeley, Reality Engine graphics, Proceedings of the 20th annual conference on Computer graphics and interactive techniques, p.109-116, September 1993 [doi>10.1145/166117.166131]
• 3: Edwin Earl Catmull, A subdivision algorithm for computer display of curved surfaces., 1974
• 4: Michael Deering , Stephanie Winner , Bic Schediwy , Chris Duffy , Neil Hunt, The triangle processor and normal vector shader: a VLSI system for high performance graphics, Proceedings of the 15th annual conference on Computer graphics and interactive techniques, p.21-30, June 1988
• 5: Michael F. Deering , Scott R. Nelson, Leo: a system for cost effective 3D shaded graphics, Proceedings of the 20th annual conference on Computer graphics and interactive techniques, p.101-108, September 1993 [doi>10.1145/166117.166130]
• 6: Deering, Michael. Data Complexity for Virtual Reality: Where do all the Triangles Go? Proceedings of IEEE VRAIS '93 (Seattle, WA, Sept. 18-22, 1993). 357-363.
• 7: Demetrescu, S. A VLSI-Based Real-Time Hidden-Surface Elimination Display System, Master's Thesis, Dept. of Com-puter Science, California Institute of Technology, Pasadena CA, May 1980.
• 8: Demetrescu, S. High Speed Image Rasterization Using Scan Line Access Memories. Proceedings of 1985 Chapel Hill Con-ference on VLSI, pages 221-243. Computer Science Press, 1985.
• 9: Fuchs, Henry, and J. Poulton. Pixel Planes: A VLSI-Orient-ed Design for a Raster Graphics Engine. In VLSI Design, 2,3 (3rd quarter 1981), 20-28.
• 10: James D. Foley , Andries van Dam , Steven K. Feiner , John F. Hughes, Computer graphics: principles and practice (2nd ed.), Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
• 11: Nader Gharachorloo , Satish Gupta , Erden Hokenek , Peruvemba Balasubramanian , Bill Bogholtz , Christian Mathieu , Christos Zoulas, Subanosecond pixel rendering with million transistor chips, Proceedings of the 15th annual conference on Computer graphics and interactive techniques, p.41-49, June 1988
• 12: N. Gharachorloo , S. Gupta , R. F. Sproull , I. E. Sutherland, A characterization of ten rasterization techniques, Proceedings of the 16th annual conference on Computer graphics and interactive techniques, p.355-368, July 1989
• 13: Andy Goris , Bob Fredrickson , Harold L. Baeverstad, Jr., A configurable pixel cache for fast image generation, IEEE Computer Graphics and Applications, v.7 n.3, p.24-32, March 1987 [doi>10.1109/MCG.1987.276962]
• 14: Chandlee B. Harrell , Farhad Fouladi, Graphics rendering architecture for a high performance desktop workstation, Proceedings of the 20th annual conference on Computer graphics and interactive techniques, p.93-100, September 1993 [doi>10.1145/166117.166129]
• 15: M5M410092 FBRAM Specification. Mitsubishi Electric, 1994.
• 16: Steven Molnar , John Eyles , John Poulton, PixelFlow: high-speed rendering using image composition, ACM SIGGRAPH Computer Graphics, v.26 n.2, p.231-240, July 1992
• 17: David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
• 18: Pinkham, R., M. Novak, and K. Guttag. Video RAM Excels at Fast Graphics. In Electronic Design 31,17, Aug. 18, 1983, 161-182.
• 19: R. F. Sproull , I. Sutherland , A. Thomson , S. Gupta , C. Minter, The 8 by 8 display, ACM Transactions on Graphics (TOG), v.2 n.1, p.32-56, Jan. 1983 [doi>10.1145/357314.357316]
• 20: Whitton, Mary. Memory Design for Raster Graphics Dis-plays. In IEEE CG&A 4,3 (March 1984), 48-65, 1984.

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.3 COMPUTER GRAPHICS

Additional Classification:
  I. Computing Methodologies
  I.3 COMPUTER GRAPHICS

General Terms:
Design, Measurement, Theory

Keywords:
3D graphics hardware, caching, dynamic memory, parallel graphics algorithms, rendering