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Power analysis of embedded software: a first step towards software power minimization
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Source International Conference on Computer Aided Design archive
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 384 - 390  
Year of Publication: 1994
ISBN:0-89791-690-5
Authors
Vivek Tiwari  Dept. of Electrical Engineering, Princeton University, Princeton, NJ
Sharad Malik  Dept. of Electrical Engineering, Princeton University, Princeton, NJ
Andrew Wolfe  Dept. of Electrical Engineering, Princeton University, Princeton, NJ
Sponsors
IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 41,   Downloads (12 Months): 127,   Citation Count: 21
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ABSTRACT

Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical component of the design specification of these systems. At present, however, power analysis tools can only be applied at the lower levels of the design—the circuit or gate level. It is either impractical or impossible to use the lower level tools to estimate the power cost of the software component of the system. This paper describes the first systematic attempt to model this power cost. A power analysis technique is developed that has been applied to two commercial microprocessors—Intel 486DX2 and Fujitsu SPARClite 934. This technique can be employed to evaluate the power cost of embedded software and also be used to search the design space in software power optimization.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Intel Corp. i~86 Microprocessor, Hardware Reference Manual, 1990.
 
2
 
3
C. L. Su, C. Y. Tsui, and A. M. Despain. Low power architecture design and compilation techniques for high-performance processors. In IEEE COMPCON, Feb. 1994.
 
4
V. Tiwari, T.C. Lee, M. Fujita, and D. Maheshwari. Power analysis of the SPARClite MB86934. Technical Report FLA-CAD-94-01, Fujitsu Labs of America, August 1994.
 
5
V. Tiwari, S. Malik, and A. Wolfe. Compilation techniques for low energy: An overview. In Proceedings of lhe 199/t Symposium on Low Power Electronics, October 1994.
 
6
V. Tiwari, S. Malik, and A. Wolfe. Power analysis of the Intel 486DX2. Technical Report CE-M94-5, Princeton Univ., Dept. of Elect. Eng., June 1994.

CITED BY  21

Collaborative Colleagues:
Vivek Tiwari: colleagues
Sharad Malik: colleagues
Andrew Wolfe: colleagues