Process-variation-tolerant clock skew minimization

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Process-variation-tolerant clock skew minimization

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International Conference on Computer Aided Design archive
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 284 - 288

Year of Publication: 1994

ISBN:0-89791-690-5

Authors

Shen Lin	IBM T.J. Watson Research Center, Yorktown Heights, NY
C. K. Wong	IBM T.J. Watson Research Center, Yorktown Heights, NY

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 24, Citation Count: 9

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

In this paper, we propose a novel hierarchical multiple-merge zero skew clock routing algorithm. The routing results produced by our approach will have zero skew in the nominal case and minimal skew increase in the presence of worst process variations. In order to construct such a clock routing, we formulate the linear placement with maximum spread problem and provide an O(nmin{n,P}lognlogP) algorithm for optimally solving this problem, where n is the number of cells to be placed and P is the maximum spread. Experimental results show that our algorithm can indeed reduce the skew in various manufacturing variations effectively.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 9

	Jason Cong , Andrew B. Kahng , Cheng-Kok Koh , C.-W. Albert Tsao, Bounded-skew clock and Steiner routing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.341-388, July 1998
	Jae W. Chung , De-Yu Kao , Chung-Kuan Cheng , Ting-Ting Lin, Optimization of power dissipation and skew sensitivity in clock buffer synthesis, Proceedings of the 1995 international symposium on Low power design, p.179-184, April 23-26, 1995, Dana Point, California, United States
	Haihua Su , Sachin S. Sapatnekar, Hybrid structured clock network construction, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Josè Luis Neves , Eby G. Friedman, Buffered Clock Tree Synthesis with Non-Zero Clock Skew Schedulingfor Increased Tolerance to Process Parameter Variations, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.149-161, June/July 1997
	Jeng-Liang Tsai , Charlie Chung-Ping Chen, Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Anand Rajaram , Jiang Hu , Rabi Mahapatra, Reducing clock skew variability via cross links, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Anand Rajaram , David Z. Pan , Jiang Hu, Improved algorithms for link-based non-tree clock networks for skew variability reduction, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Bing Lu , Jiang Hu , Gary Ellis , Haihua Su, Process variation aware clock tree routing, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	W.-C. D. Lam , J. Jam , C.-K. Koh , V. Balakrishnan , Y. Chen, Statistical based link insertion for robust clock network design, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.588-591, November 06-10, 2005, San Jose, CA