Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback
Take a look at the new version of this page: [ beta version ]. Tell us what you think.

Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics

Full text

Pdf (448 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 190 - 194

Year of Publication: 1994

ISBN:0-89791-690-5

Authors

A. Dharchoudhury	Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
S. M. Kang	Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
K. H. Kim	CAE Department, Samsung Electronics Co., Seoul, S. Korea
S. H. Lee	CAE Department, Samsung Electronics Co., Seoul, S. Korea

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 7, Citation Count: 8

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

ABSTRACT

This paper presents a technique called regionwise quadratic (RWQ) modeling that allows highly accurate MOS models, as well as measured I-V data, to be used in fast timing simulation. This technique significantly increases the accuracy of fast timing simulation while maintaining efficiency by permitting analytical solutions of node equations. A fast timing simulator using these RWQ models has been implemented. Several examples of RWQ modeling are provided, and comparisons of simulation results with SPICE3 are shown to demonstrate accuracy and efficiency. Speedups of two to three orders of magnitude for circuits containing up to 2000 transistors are observed.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	David Vincent Overhauser, Fast timing simulation of mos vlsi circuits, 1989
	2	Y.-H. Shih, Y. Leblebici, and S. M. Kang, "ILLI- ADS: A fast timing and reliability simulator for digital MOS circuits," IEEE Trans. Computer-Aided Design, vol. 12(9), pp. 1387-1402, Sept. 1993.
	3	Y. H. Shih and S. M. Kang, "Analytic transient solution of general MOS circuit primitives," IEEE Trans. Computer-Aided Design, vol. 11(6), pp. 719-731, June 1992.
	4	Yu-Hsu Chang , Andrew T. Yang, Analytic macromodeling and simulation fo tightly-coupled mixed analog-digital circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.244-247, November 1992, Santa Clara, California, United States
	5	W. T. Cheng and S. Davidson, "Sequential circuit test generator (STG) benchmark results," Proc. IEEE Int. Syrup. on Circuits and Systems, pp. 1938-1941, May 1989.

CITED BY 8

	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002
	Yi-Kan Cheng , Chin-Chi Teng , Abhijit Dharchoudhury , Elyse Rosenbaum , Sung-Mo Kang, ICET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips, Proceedings of the 33rd annual conference on Design automation, p.548-551, June 03-07, 1996, Las Vegas, Nevada, United States
	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States
	S. Gavrilov , A. Glebov , S. Pullela , S. C. Moore , A. Dharchoudhury , R. Panda , G. Vijayan , D. T. Blaauw, Library-less synthesis for static CMOS combinational logic circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.658-662, November 09-13, 1997, San Jose, California, United States
	A. Dharchoudhury , S. M. Kang , H. Cha , J. H. Patel, Fast timing simulation of transient faults in digital circuits, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.719-722, November 06-10, 1994, San Jose, California, United States
	Zhong Wang , Jianwen Zhu, Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching, Proceedings of the conference on Design, Automation and Test in Europe, p.11026, March 03-07, 2003
	Yi-Kan Cheng , Elyse Rosenbaum , Sung-Mo Kang, ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits, Proceedings of the 1996 European conference on Design and Test, p.566, March 11-14, 1996
	Mohammad J. Mahjoob , Majid Abdollahzade , Reza Zarringhalam , Ahmad Kalhor, Chaotic time series forecasting using locally quadratic fuzzy neural models, Proceedings of the 9th WSEAS International Conference on Fuzzy Systems, p.26-32, May 02-04, 2008, Sofia, Bulgaria