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Dataflow-driven memory allocation for multi-dimensional signal processing systems
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Source International Conference on Computer Aided Design archive
Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 31 - 34  
Year of Publication: 1994
ISBN:0-89791-690-5
Authors
Florin Balasa  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Francky Catthoor  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Hugo De Man  IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Sponsors
IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 11,   Citation Count: 21
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ABSTRACT

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing systems. In this paper, a novel background memory allocation and assignment technique is presented. It is intended for a behavioural algorithm specification, where the procedural ordering of the memory related operations is not yet fully fixed. Instead of the more restricted classical scheduling-based explorations, starting from procedurally interpreted specifications in terms of loops, a novel optimization approach—driven by data flow analysis—is proposed. Employing the estimated silicon area as a steering cost, this allocation/assignment technique yields one or (optionally) several distributed (multi-port) memory architecture(s) with fully-determined characteristics, complying with a given clock cycle budget for read/write operations. Moreover, our approach can accurately deal with complex multi-dimensional signals by means of a polyhedral data-flow analysis operating with groups of scalars.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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I.Ahmad, C.Y.R.Chen, "Post-processor for data path synthesis using multiport memories," Proc. ICCAD'91, pp.276-279, Santa Clara CA, Nov. 1991.
 
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F.Franssen, L.Nachtergaele, H.Samsom, F.Catthoor, H.De Man, "Control flow optimization for fast system simulation and storage minimization", Proc. 5th EDAC'9~, pp.20-24, Paris, France, Mar. 1994.
 
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G.Goossens, J.Rabaey, J.VandewMle, H.De Man, "An efficient microcode compiler for application-specific DSP processors," IEEE Trans. CAD, pp.925-937, Sep. 1990.
 
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J.M.Mulder, N.T.Quach, M.J.Flynn, "An Area Model for On-Chip Memories and its Application," IEEE J. Solid-state Circ., Vol.SC-26, pp.98-105, Feb. 1991.
 
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L.Ramachandran, D.Gajski, V.Chaiyakul, "An algorithm for array variable clustering," Proc. 5th EDA C'9~, pp.262-266, Paris, France, Feb. 1994.
 
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L.Stok, J.Jess, "Foreground memory management in data path synthesis," Int. J. on Circ. Theory and Appl., Vol.20, pp.235-255, 1992.
 
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CITED BY  21

Collaborative Colleagues:
Florin Balasa: colleagues
Francky Catthoor: colleagues
Hugo De Man: colleagues