Critical issues regarding HPS, a high performance microarchitecture

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Critical issues regarding HPS, a high performance microarchitecture

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International Symposium on Microarchitecture archive
Proceedings of the 18th annual workshop on Microprogramming table of contents

Pacific Grove, California, United States

Pages: 109 - 116

Year of Publication: 1985

ISBN:0-89791-172-5

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Authors

Y. N. Patt	Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA
S. W. Melvin	Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA
W. M. Hwu	Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA
M. C. Shebanow	Computer Science Diuiaion, University of Calqornia, Berkeley, Berkeley, CA

Sponsor

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 29, Citation Count: 24

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

HPS is a new model for a high performance microarchitecture which is targeted for implementing very dissimilar ISP architectures. It derives its performance from executing the operations within a restricted window of a program out-of-order, asynchronously, and concurrently whenever possible. Before the model can be reduced to an effective working implementation of a particular target architecture, several issues need to be resolved. This paper discusses these issues, both in general and in the context of architectures with specific characteristics.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Y. N. Patt , W. M. Hwu , M. Shebanow, HPS, a new microarchitecture: rationale and introduction, Proceedings of the 18th annual workshop on Microprogramming, p.103-108, December 03-06, 1985, Pacific Grove, California, United States
	2	Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Rceearch and Development, vol. 11, 1967, pp, 25-33.

CITED BY 24

	Eric Hao , Po-Yung Chang , Marius Evers , Yale N. Patt, Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures, International Journal of Parallel Programming, v.26 n.4, p.449-478, August 1998
	Eric Hao , Po-Yung Chang , Marius Evers , Yale N. Patt, Increasing the instruction fetch rate via block-structured instruction set architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.191-200, December 02-04, 1996, Paris, France
	W. Hwu , Y. N. Patt, HPSm, a high performance restricted data flow architecture having minimal functionality, ACM SIGARCH Computer Architecture News, v.14 n.2, p.297-306, June 1986
	Monica S. Lam , Robert P. Wilson, Limits of control flow on parallelism, ACM SIGARCH Computer Architecture News, v.20 n.2, p.46-57, May 1992
	Stephen Melvin , Yale Patt, Exploiting fine-grained parallelism through a combination of hardware and software techniques, ACM SIGARCH Computer Architecture News, v.19 n.3, p.287-296, May 1991
	Ramesh Radhakrishnan , Deependra Talla , Lizy Kurian John, Allowing for ILP in an embedded Java processor, ACM SIGARCH Computer Architecture News, v.28 n.2, p.294-305, May 2000
	Y. N. Patt , W. M. Hwu , M. Shebanow, HPS, a new microarchitecture: rationale and introduction, ACM SIGMICRO Newsletter, v.16 n.4, p.103-108, Dec. 1985
	Michael Butler , Yale Patt, A comparative performance evaluation of various state maintenance mechanisms, Proceedings of the 26th annual international symposium on Microarchitecture, p.70-79, December 01-03, 1993, Austin, Texas, United States
	Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, ACM SIGARCH Computer Architecture News, v.19 n.3, p.276-286, May 1991
	Mark Smotherman , Manoj Franklin, Improving CISC instruction decoding performance using a fill unit, Proceedings of the 28th annual international symposium on Microarchitecture, p.219-229, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	Sriram Vajapeyam , Tulika Mitra, Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences, ACM SIGARCH Computer Architecture News, v.25 n.2, p.1-12, May 1997
	Wen-mei W. Hwu , Yale N. Patt, Retrospective: HPSm, a high performance restricted data flow architecture having minimal functionality, 25 years of the international symposia on Computer architecture (selected papers), p.43-44, June 27-July 02, 1998, Barcelona, Spain
	Michael Butler , Yale Patt, The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling, Proceedings of the 24th annual international symposium on Microarchitecture, p.34-41, September 1991, Albuquerque, New Mexico, Puerto Rico
	Meng-chou Chang , Feipei Lai, Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme, IEEE Transactions on Computers, v.45 n.3, p.278-293, March 1996
	Po-Yung Chang , Eric Hao , Yale N. Patt , Pohua P. Chang, Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.99-108, June 27-29, 1995, Limassol, Cyprus
	Michael Butler , Yale Patt, An investigation of the performance of various dynamic scheduling techniques, ACM SIGMICRO Newsletter, v.23 n.1-2, p.1-9, Dec. 1992
	Po-Yung Chang , Eric Hao , Yale N. Patt, Target prediction for indirect jumps, ACM SIGARCH Computer Architecture News, v.25 n.2, p.274-283, May 1997
	Y. N. Patt , S. W. Melvin , W. M. Hwu , M. C. Shebanow , C. Chen, Run-time generation of HPS microinstructions from a VAX instruction stream, ACM SIGMICRO Newsletter, v.17 n.4, p.75-81, Dec. 1986
	Manoj Franklin , Gurindar S. Sohi, ARB: A Hardware Mechanism for Dynamic Reordering of Memory References, IEEE Transactions on Computers, v.45 n.5, p.552-571, May 1996
	Simha Sethumadhavan , Rajagopalan Desikan , Doug Burger , Charles R. Moore , Stephen W. Keckler, Scalable Hardware Memory Disambiguation for High-ILP Processors, IEEE Micro, v.24 n.6, p.118-127, November 2004
	Gurindar S. Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, v.39 n.3, p.349-359, March 1990
	Yale N. Patt , Sanjay J. Patel , Marius Evers , Daniel H. Friendly , Jared Stark, One Billion Transistors, One Uniprocessor, One Chip, Computer, v.30 n.9, p.51-57, September 1997
	A. Despain , Y. Patt , V. Srini , P. Bitar , W. Bush , C. Chien , W. Citrin , B. Fagin , W. Hwu , S. Melvin , R. McGeer , A. Singhal , M. Shebanow , P. Van Roy, Aquarius, ACM SIGARCH Computer Architecture News, v.15 n.1, p.22-34, March 1987
	Simha Sethumadhavan , Rajagopalan Desikan , Doug Burger , Charles R. Moore , Stephen W. Keckler, Scalable Hardware Memory Disambiguation for High ILP Processors, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.399, December 03-05, 2003