| HPS, a new microarchitecture: rationale and introduction |
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International Symposium on Microarchitecture
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Proceedings of the 18th annual workshop on Microprogramming
table of contents
Pacific Grove, California, United States
Pages: 103 - 108
Year of Publication: 1985
ISBN:0-89791-172-5
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Authors
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Y. N. Patt
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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W. M. Hwu
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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M. Shebanow
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Downloads (6 Weeks): 2, Downloads (12 Months): 56, Citation Count: 60
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 ABSTRACT
HPS (High Performance Substrate) is a new microarchitecture targeted for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. This paper introduces the model, provides the rationale for its selection, and describes the data path and flow of instructions through the microengine.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Anderson, D. W., Sparacio, F. J., Tomasulo, R. M., "The IBM Systed360 Model 91: Machine Philosophy and Instruction - Handling," IBM Journal of Research and Development, Vol. 11, No. 1, 1967, pp. 8-24.
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Arvind and Goostelow, K. P., "A New Interpreter for Dataflow and Its Implications for Computer Architecture," Department of Information and Computer Science, University of California, Irvine, Tech. Report 72, October 1975.
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Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, 1967, pp 25 - 33. Principles and Examples, McGraw-Hill, 1982.
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Y. N. Patt , S. W. Melvin , W. M. Hwu , M. C. Shebanow, Critical issues regarding HPS, a high performance microarchitecture, Proceedings of the 18th annual workshop on Microprogramming, p.109-116, December 03-06, 1985, Pacific Grove, California, United States
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CITED BY 61
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Pohua P. Chang , William Y. Chen , Scott A. Mahlke , Wen-mei W. Hwu, Comparing static and dynamic code scheduling for multiple-instruction-issue processors, Proceedings of the 24th annual international symposium on Microarchitecture, p.25-33, September 1991, Albuquerque, New Mexico, Puerto Rico
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Daniel Holmes Friendly , Sanjay Jeram Patel , Yale N. Patt, Alternative fetch and issue policies for the trace cache fetch mechanism, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.24-33, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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Eric Hao , Po-Yung Chang , Marius Evers , Yale N. Patt, Increasing the instruction fetch rate via block-structured instruction set architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.191-200, December 02-04, 1996, Paris, France
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Augustus K. Uht , Constantine D. Polychronopoulos , John F. Kolen, On the combination of hardware and software concurrency extraction methods, Proceedings of the 20th annual workshop on Microprogramming, p.133-141, December 01-04, 1987, Colorado Springs, Colorado, United States
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Stephen Jourdan , Ronny Ronen , Michael Bekerman , Bishara Shomar , Adi Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.216-225, November 1998, Dallas, Texas, United States
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Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, ACM SIGARCH Computer Architecture News, v.19 n.3, p.276-286, May 1991
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Hagit Attiya , Soma Chaudhuri , Roy Friedman , Jennifer L. Welch, Shared memory consistency conditions for non-sequential execution: definitions and programming strategies, Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures, p.241-250, June 30-July 02, 1993, Velen, Germany
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Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, 25 years of the international symposia on Computer architecture (selected papers), p.408-417, June 27-July 02, 1998, Barcelona, Spain
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Po-Yung Chang , Eric Hao , Yale N. Patt , Pohua P. Chang, Using predicated execution to improve the performance of a dynamically scheduled machine with speculative execution, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.99-108, June 27-29, 1995, Limassol, Cyprus
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William Mangione-Smith , Santosh G. Abraham , Edward S. Davidson, Register requirements of pipelined processors, Proceedings of the 6th international conference on Supercomputing, p.260-271, July 19-24, 1992, Washington, D. C., United States
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James E. Wilson , Steve Melvin , Michael Shebanow , Wen-mei Hwu , Yale N. Patt, On tuning the microarchitecture of an HPS implementation of the VAX, Proceedings of the 20th annual workshop on Microprogramming, p.162-167, December 01-04, 1987, Colorado Springs, Colorado, United States
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B. Ramakrishna Rau , David W. L. Yen , Wei Yen , Ross A. Towie, The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs, Computer, v.22 n.1, p.12-26, 28-30, 32-35, January 1989
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Yale N. Patt , Sanjay J. Patel , Marius Evers , Daniel H. Friendly , Jared Stark, One Billion Transistors, One Uniprocessor, One Chip, Computer, v.30 n.9, p.51-57, September 1997
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A. Despain , Y. Patt , V. Srini , P. Bitar , W. Bush , C. Chien , W. Citrin , B. Fagin , W. Hwu , S. Melvin , R. McGeer , A. Singhal , M. Shebanow , P. Van Roy, Aquarius, ACM SIGARCH Computer Architecture News, v.15 n.1, p.22-34, March 1987
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