Stack processing techniques in delayed-staging storage hierarchies

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Stack processing techniques in delayed-staging storage hierarchies

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Communications of the ACM archive
Volume 26 , Issue 11 (November 1983) table of contents

Pages: 999 - 1007

Year of Publication: 1983

ISSN:0001-0782

Author

Gabriel M. Silberman

Technion—Israel Institute of Technology, Israel

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 17, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Chow, C.K. On optimization of storage hierarchies. IBM I. Res. and Develop. 18, 3 (May 1974). 194-203.
	2	Chow, C.K. Determination of cache's capacity and its matching storage hierarchy. IEEE Trans. Comp. C-25, 2 (Feb. 1976), 157-164.
	3	Edward G. Coffman, Jr. , Peter J. Denning, Operating Systems Theory, Prentice Hall Professional Technical Reference, 1973
	4	Duffin, R.J., Peterson, E.L., and Zener, C. Geometric Programming. Wiley, New York. 1967.
	5	Gecsei, J. Determining hit ratios for multilevel hierarchies. IBM I. Res. and Develop. 18, 4 (July 1974), 316-327.
	6	Mattson, R.L., Gecsei, L. Slutz, D.R.. and Traiger, I.L. Evaluation techniques for storage hierarchies. IBM Syst. 1. 9, 2 (1970). 78-117.
	7	Mattson, R.L. Evaluation of multilevel memories. IEEE Trans. Magnetics MAG-7.4 (Dec. 1971). 814-'819.
	8	Silberman. G.M. Delayed-staging storage hierarchies and the active memory unit concept. Ph,D. Thesis, SUNY at Buffalo, July 1980.
	9	Silberman, G.M. Determining fault ratios in multilevel delayed-staging storage hierarchies. IEEE Trans. Comp. C-31.4 (April 1982). 305- 310.
	10	Silberman. G.M. Delayed-staging hierarchy optimization, to appear, IEEE Trans. Comp.
	11	Stutz, D.R., and Traiger. I.L. Determination of hit ratios for a class of staging hierarchies. San Jose. California: IBM. Res. Rep. RJ-1044. May 1972.
	12	Alan Jay Smith, Characterizing the Storage Process and Its Effect on the Update of Main Memory by Write Through, Journal of the ACM (JACM), v.26 n.1, p.6-27, Jan. 1979 [doi>10.1145/322108.322110]
	13	Smith, A.J. Sequential program prefetching in memory hierarchies. IEEE Computer 11, 12 (Dec. 1978), 167-169.
	14	Traiger, I.L.. and Slutz, D.R. One-pass techniques for the evaluation of memory hierarchies. San Jose. California: IBM Res. Rep. RJ-892. July 1971.