RATCHET: real-time address trace compression hardware for extended traces

ABSTRACT

The address traces used in computer architecture research are commonly generated using software techniques that introduce time dilations of an order of magnitude or more. Such techniques may also omit classes of memory references that are important for accurate models of computer systems, such as instruction prefetches, operating system references, and interrupt activity.We describe a technique for capturing all classes of references in real time. RATCHET employs trace filtering hardware to reduce the bandwidth and storage requirements that have previously limited the usefulness of hardware-based tracing. In evaluating this technique using the ten SPEC89 benchmark programs running on a Sun-3/60 workstation, we found that a small filter cache achieves compression ratios in the 10-30 range during the startup section of the programs. Traces from the middle sections of the C programs achieved compression ratios of 20-30, while the FORTRAN codes produced ratios of 45-84. Traces from a smaller ionospheric simulator program were compressed by factors of 100.These filtered traces typically represent 36 million contiguous references.

REFERENCES

• 1: Anant Agarwal , Minor Huffman, Blocking: exploiting spatial locality for trace compaction, Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, p.48-57, April 1990, Univ. of Colorado, Boulder, Colorado, United States
• 2: Flanagan, J. K., <i>et al.</i>, "BACH: BYU Address Collection Hardware, The Collection of Complete Traces," <i>Proceedings, 6th International Conference on Modeling Techniques and Tools for Computer Performance Evaluation</i>, 1992.
• 3: Johnson, E. E., "The Virtual Port Memory GMMP Multiprocessor," <i>Proceedings, International Conference on Computing and Information:</i> 127--130, 1989.
• 4: Johnson, E. E., <i>et al.</i>, "An HF Channel and Modem Simulator Package," Technical Report NMSU ECE-91-005, New Mexcio State University, Las Cruces, New Mexico, June 1991.
• 5: S. Laha , J. H. Patel , R. K. Iyer, Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems, IEEE Transactions on Computers, v.37 n.11, p.1325-1336, November 1988 [doi>10.1109/12.8699]
• 6: Thomas Roberts Puzak, Analysis of cache replacement-algorithms, 1985
• 7: A. D. Samples, Mache: no-loss trace compaction, Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, p.89-97, May 23-26, 1989, Oakland, California, United States
• 8: Smith, A. J., "Two Methods for the Efficient Analysis of Memory Address Trace Data," <i>IEEE Transactions on Software Engineering</i>, <b>SE-3</b> (1): 1977.
• 9: Stone, H. S., <i>High-Performance Computer Architecture</i>, third edition, Addison-Wesley Publishing Company, Reading, Massachusetts, 1993.
• 10: C. B. Stunkel , W. K. Fuchs, TRAPEDS: producing traces for multicomputers via execution driven simulation, Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, p.70-78, May 23-26, 1989, Oakland, California, United States
• 11: Craig B. Stunkel , Bob Janssens , W. Kent Fuchs, Address Tracing for Parallel Machines, Computer, v.24 n.1, p.31-38, January 1991 [doi>10.1109/2.67191]
• 12: Wen-Hann Wang , Jean-Loup Baer, Efficient trace-driven simulation method for cache performance analysis, Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, p.27-36, April 1990, Univ. of Colorado, Boulder, Colorado, United States

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization

General Terms:
Design, Measurement, Performance, Theory