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Performance evaluation of hybrid hardware and software distributed shared memory protocols
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Source International Conference on Supercomputing archive
Proceedings of the 8th international conference on Supercomputing table of contents
Manchester, England
Pages: 274 - 288  
Year of Publication: 1994
ISBN:0-89791-665-4
Authors
Rohit Chandra  Computer Systems Laboratory, Stanford University, CA
Kourosh Gharachorloo  Computer Systems Laboratory, Stanford University, CA
Vijayaraghavan Soundararajan  Computer Systems Laboratory, Stanford University, CA
Anoop Gupta  Computer Systems Laboratory, Stanford University, CA
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

Hardware distributed shared memory (DSM) systems efficiently support fine grain sharing of data by maintaining coherence at the level of individual cache lines and providing automatic replication in processor caches. Software DSM systems, on the other hand, amortize high communication costs by maintaining coherence at coarser granularities and replicating data at the level of local main memories. Even though software DSM systems have traditionally been targeted towards loosely coupled environments, some of the techniques are potentially useful in the context of tightly coupled multiprocessors. In particular, communicating data at a coarse grain can sometimes be more efficient than transferring the data as individual cache lines. Furthermore, replication in local memories can accommodate applications with larger working sets as compared to replication in processor caches only. Therefore, combining the two techniques in a hybrid protocol can potentially exploit the benefits of each approach. This paper proposes one such hybrid protocol and evaluates its performance in the context of the FLASH multiprocessor architecture. The hybrid system allows the programmer to optionally identify regions of data shared at a coarse granularity. Coherence for such data is maintained at the grain of the entire region using a software-DSM-style protocol. We evaluate the performance gains of this approach through a detailed simulation study of several parallel applications. Our preliminary results show that the hybrid protocol can eliminate a substantial fraction of remote cache misses through bulk transfer of coarse grain data regions and replication of such data in local memories. The performance gains over hardware cache coherence are modest at low network latencies, but increase substantially at higher network latencies and processor speeds. Finally, we show that similar to cache-only memory architectures, the hybrid protocol is insensitive to data placement issues.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
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Jean-Loup Baer and Tien-Fu Chen, An effective on-chip preloading scheme to reduce data access penalty. Technical Report 91-03-07, University of Washington, March 1991.
 
5
B. Bershad and M. Zekauskas. Midway: Shared memory parallel programming with entry consistency for distributed memory multiprocessors. Technical Report CMU-CS-91-170~ Camegie-MeUon University, September 1991.
 
6
Brian Bershad, Matthew Zekauskas, and Wayne Sawdon. The Midway distributed shared memory system. In Proceedings of COMP- CON'93, pages 528-537, February 1993.
7
8
 
9
Rohit Chandra, Anoop Gupta, and John L. Hennessy. Integrating concurrency and data abstraction in the COOL programming language. IEEE Computer, August 1994. To appear.
10
11
12
13
14
15
16
17
18
 
19
20
21
22
23
24
 
25
Leslie Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28(9):690--691, September 1979.
26
 
27
28
29
 
30
31
 
32
Kendall Square Research. KSR1 Technical Summary. Waltham, MA, 1992.
 
33
Martin Rinard. The Design and Implementation of Jade, a high-level Portable Parallel Programming Language. PhD thesis, Department of Computer Science, Stanford University. In preparation.
 
34
 
35
 
36
Edward Rothberg and Anoop Gupta. An efficient block-oriented approach to parallel sparse cholesky factorization. Technical Report CSL-TR-92-533, Computer Systems Lab, Stanford University, July 1992.
37
38
39
 
40
Josep Torrellas, Monica Lam, and John Hennessy. Shared data placement optimizat~ons to reduce multiprocessor cache miss rates. In Proceedings of the 1990 International Conference on Parallel Processing, pages II: 266-270, August 1990.
 
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Collaborative Colleagues:
Rohit Chandra: colleagues
Kourosh Gharachorloo: colleagues
Vijayaraghavan Soundararajan: colleagues
Anoop Gupta: colleagues