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Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments
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Source International Conference on Supercomputing archive
Proceedings of the 8th international conference on Supercomputing table of contents
Manchester, England
Pages: 166 - 175  
Year of Publication: 1994
ISBN:0-89791-665-4
Authors
Eric L. Boyd  Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan
Edward S. Davidson  Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

We have developed an automatic technique for evaluating the communication performance of massively parallel processors (MPPs). Both communication latency and the amount of communication are investigated as a function of a few basic parameters that characterize an application workload. Parameter values are captured in an automatically generated sparse matrix that multiplies a dense vector in the synthetic workload. Our approach is capable of explaining the degradation of processor performance caused by communication. Using the Kendall Square Research KSR1 MPP as a case study, we demonstrate the effectiveness of the technique through a series of experiments used to characterize the communication performance. We show that read and write communciation latencies vary from 150 to 180 and from 80 to 100 processor cycles, respectively. We show that the read communication latency approximates a linear function of the total system communciation (in subpages), write communication approximates a linear function of the number of distinct shared subpages, and that KSR's automatic update feature is effective in reducing the number of read communications given careful binding of threads to processors.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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W.H. Mangione-Smith, T-P. Shih, S. G. Abraham, E. S. Davidson, "Approaching a Machine-Application Bound in Delivered Performance on Scientific Code," IEEE Proceedings, August, 1993, pp. 1166-1178.
 
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W. Azeem. "Modeling and Approaching the Deliverable Performance Capability of the KSR1 Processor," University of Michigan, Technical Report, CSE-TR-164-93, June, 1993.
 
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E.L. Boyd, W. Azeem, H-H. Lee, T-P. Shih, S-H. Hung, E. S. Davidson. "A Hierarchial Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1," to apper in the Proceedings of the 1994 International Conference on Parallel Processing.
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K. Harzallah, H. Li, K. Sevcik. "Evaluating the Effect of the Auto-Update on the Kendall Square KSR1," Computer Systems Research Institute University of Toronto Technical Report CSRI-291, October, 1993.
 
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T.D. Wagner, E. Smirni, A. W. Apon, M. Madhukar, L. W. Dowdy. "Measuring the Effects of Thread Placement on the Kendall Square KSR1," Oak Ridge National Laboratory Technical Report ORNL/TM-12462, August, 1993.
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KSR1 Principles of Operation, Kendall Square Research Corporation, Waltham, MA, 1992.
 
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KSR1 Technical Summary, Kendall Square Research Corporation, Waltham, MA, 1992.
 
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T. H. Dunign. "Kendall Square Mdtiprocessor: Early experiences and performance," Oak Ridge National Laboratory Technical Report ORNL/TM-12065, April, 1992.
 
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D. Windheiser, E. L. Boyd, E. Hao, S. G. Abraham, E. S. Davidson. "KRS1 Multiprocessor, Analysis of Latency Hiding Techniques in a Sparse Solver," Proceedings of the 7th International Parallel Processing Symposium, April, 1993, pp. 454-461.
 
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Collaborative Colleagues:
Eric L. Boyd: colleagues
Edward S. Davidson: colleagues