SIMD instruction cache

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SIMD instruction cache

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ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures table of contents

Cape May, New Jersey, United States

Pages: 67 - 75

Year of Publication: 1994

ISBN:0-89791-671-9

Author

Todd E. Rockoff

Discipline of Computer Science, Flinders University, GPO Box 2100, Adelaide 5001 SA, AUSTRALIA

Sponsors

SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
European Comp Soc : European Computer Society

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 21, Citation Count: 0

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ABSTRACT

SIMD instruction cache (or I-cache) is proposed to remedy a heretofore un-compensated instruction delivery rate limitation of SIMD computers. This paper introduces the concept of SIMD I-cache and sketches the I-cache design space. On the basis of throughput using chip area as a hardware cost constraint, detailed evaluations of simple I-cache variants for a diverse set of sample problems are presented. Simple I-cache variants occupy negligible area in chips while providing significant speedups, even for problems ordinarily thought to be inherently communication-bound. These results suggest that I-cached SIMD computers exhibit the highest throughput of any multiprocessors for scalable data-parallel problems.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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