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Model checking and modular verification
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Source ACM Transactions on Programming Languages and Systems (TOPLAS) archive
Volume 16 ,  Issue 3  (May 1994) table of contents
Pages: 843 - 871  
Year of Publication: 1994
ISSN:0164-0925
Authors
Orna Grumberg  Technion–Israel Institute of Technology, Haifa, Israel
David E. Long  Carnegie Mellon Univ., Pittsburgh, PA
Publisher
ACM  New York, NY, USA
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ABSTRACT

We describe a framework for compositional verification of finite-state processes. The framework is based on two ideas: a subset of the logic CTL for which satisfaction is preserved under composition, and a preorder on structures which captures the relation between a component and a system containing the component. Satisfaction of a formula in the logic corresponds to being below a particular structure (a tableau for the formula) in the preorder. We show how to do assume-guarantee-style reasoning within this framework. Additionally, we demonstrate efficient methods for model checking in the logic and for checking the preorder in several special cases. We have implemented a system based on these methods, and we use it to give a compositional verification of a CPU controller.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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BEN-ARI, M., MANNA, Z., AND PNUELI, A. 1983. The temporal logic of branching time. Acta Informatica 20, 207-226.
 
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CITED BY  58


REVIEW

"Ramaswamy Ramanujam : Reviewer"

When reasoning about systems of parallel processes, verifying global properties requires construction of the global state space, whose size is typically exponential in the number of processes. Avoiding this state explosion is a central problem  more...

Collaborative Colleagues:
Orna Grumberg: colleagues
David E. Long: colleagues