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Sequential consistency versus linearizability
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Source ACM Transactions on Computer Systems (TOCS) archive
Volume 12 ,  Issue 2  (May 1994) table of contents
Pages: 91 - 122  
Year of Publication: 1994
ISSN:0734-2071
Authors
Hagit Attiya  Technion–Israel Institute of Technology, Haifa, Israel
Jennifer L. Welch  Univ. of North Carolina, Chapel Hill
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 28,   Downloads (12 Months): 135,   Citation Count: 33
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ABSTRACT

The power of two well-known consistency conditions for shared-memory multiprocessors, sequential consistency and linearizability, is compared. The cost measure studied is the worst-case response time in distributed implementations of virtual shared memory supporting one of the two conditions. Three types of shared-memory objects are considered: read/write objects, FIFO queues, and stacks. If clocks are only approximately synchronized (or do not exist), then for all three object types it is shown that linearizability is more expensive than sequential consistency. We show that, for all three data types, the worst-case response time is very sensitive to the assumptions that are made about the timing information available to the system. Under the strong assumption that processes have perfectly synchronized clocks, it is shown that sequential consistency and linearizability are equally costly. We present upper bounds for linearizability and matching lower bounds for sequential consistency. The upper bounds are shown by presenting algorithms that use atomic broadcast in a modular fashion. The lower-bound proofs for the approximate case use the technique of “shifting,” first introduced for studying the clock synchronization problem.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
ADVE, S., AND HILL, M. 1990a. Implementing sequential consistency in cache-based systems. In Proceedings of the International Conference on Parallel Processing. Pennsylvania State University, University Park, pp. 1-47-I-50.
2
3
 
4
AHAMAD, M., Hu~ro, P. AND JOHN, R. 1990. Implementing and programming causal distributed shared memory, Tech. Rep. GIT-CC-90-49, Georgia Inst. of Technology, Atlanta, Dec.
5
 
6
7
8
9
10
 
11
12
 
13
BISIANI, R., NOWATZYK, A., AND RAVISHANKAR, M. 1989. Coherent shared memory on a distributed memory machine. In Proceedings of the International Conference on Parallel Processing. Pennsylvania State University, University Park, pp. 1-133-I-141.
 
14
BRANTLEY, W., McAULIFFE, K., AND WEISS, J. 1985. RP3 processor-memory element. In Proceedings of the International Conference on Parallel Processing (Aug. 20-23). Pennsylvania State University, University Park, pp. 782 789.
 
15
CENSIER, L. M., AND FEAUTRIER, P. 1978. A new solution to coherence problems in multicache systems. IEEE Trans. Comput. C~27, 12 (Dec.), 1112 1118.
16
 
17
COLLIER, W. W. 1984. Architectures for systems of parallel processes. Tech. Rep. 00.3253, IBM, Poughkeepsie, N.Y., Jan.
 
18
19
 
20
21
 
22
GARCIA-MOLINA, H., AND SPAUSTER, A. 1989. Message ordering in a multicast environment. In Proceedings of the Internatmnal Conference on Distributed Computing Systems (Newport Beach, Calif., June 5-9). IEEE, Los Angeles, pp. 354-361.
23
24
 
25
GOTTLmB, A ~ GRISHMAN, R., KRUSKAL~ C. K., MCAULIFFE, K. P., RUDOLPh, L., AND SNm, M. 1983. The NYU ultracomputer--Designing a MIMD shared-memory parallel computer. IEEE Trans. Comput. C-32 3 (Feb.) 175-189.
 
26
27
28
 
29
HUTTO, r., AND AHAMAD, M. 1989. Slow memory: Weakening consistency to enhance concurrency in distributed shared memories. Tech. Rep. GIT-ICS-89/39, Georgia Inst. of Technology, Atlanta, Oct.
 
30
 
31
LAMPORT, L. 1979. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput. C-28, 9 (Sept.), 690-691.
 
32
LAMPORT, L. 1986. On interprocess communication. Parts I and II. Distr~b. Comput. 1, 2, 77 101.
 
33
LmTON, R., AND SANDBERG, J. 1988. PRAM. A scalable shared memory. Tech. Rep. CS-TR-180- 88, Dept. of Computer Science, Princeton Univ., Princeton, N.J., Sept.
 
34
LUNDELIUS, J., AND LYNCH, N. 1984. An upper and lower bound for clock synchronization. Inf. Control 62, 2 3 (Aug/Sept.), 190 204.
 
35
 
36
MIN, S.. AND BAER, J. 1989 A tlmestamp-based cache coherence scheme. In Proceedings of the International Conference on Parallel Processing Pennsylvania State University, Umversity Park, pp. 1-23-I-32.
37
 
38
 
39
RAMACHANDRAN, U., AHAMAD, J., AND K~ALIDI, M.Y. 1989. Coherence of distributed shared memory: Uniiying synchronization and data transfer In Proceedings of the International Conference on Parallel Processing. Pennsylvania State University, University Park, pp. II-160-II-169.
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CITED BY  33


REVIEW

"David Michael Bowen : Reviewer"

Two different conditions for modeling concurrent access to shared data are in common use: sequential consistency and linearizability. The two are quite similar and, at times, have even been confused, but linearizability is a stronger condition  more...

Collaborative Colleagues:
Hagit Attiya: colleagues
Jennifer L. Welch: colleagues