The PowerPC performance modeling methodology

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The PowerPC performance modeling methodology

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Communications of the ACM archive
Volume 37 , Issue 6 (June 1994) table of contents

Pages: 47 - 55

Year of Publication: 1994

ISSN:0001-0782

Author

Ali Poursepanj

IBM Somerset Design Center, Austin, TX

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 4, Downloads (12 Months): 25, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	2	Johnson, M. Superscalar Microprocessor Design. Prentice-Hall, Englewood Cliffs, N.J,, t 991.
	3	S. Laha , J. H. Patel , R. K. Iyer, Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems, IEEE Transactions on Computers, v.37 n.11, p.1325-1336, November 1988 [doi>10.1109/12.8699]
	4	Liu, I., and peir, J. Cache sampling by sets. IEEE Trans. VLSI Syst. 1,2 (1993), 98-- 105,
	5	Poursepanj. A,. et. al. The power PC 603 microprocessor: Performance analysis and design trade-offs. In Proceedings of COMPCON 1994 (Feb. 1994),
	6	Poursepanj, A., and Wu, C. "Trace sam pling lot design tradeoffs of micropro cessors using SPEC 92 Integer benchmarks IBM "Tech. Rep
	7	The Power PC Visual Simulator for RISC System/6000, IBM Corporation.
	8	SPEC 92 Release notes, System Perfmance Evaluation Corporation.
	9	Craig B. Stunkel , Bob Janssens , W. Kent Fuchs, Address Tracing for Parallel Machines, Computer, v.24 n.1, p.31-38, January 1991 [doi>10.1109/2.67191]

CITED BY 10

	Bryan Black , John Paul Shen, Calibration of Microprocessor Performance Models, Computer, v.31 n.5, p.59-65, May 1998
	Lieven Eeckhout , Koen De Bosschere, Efficient simulation of trace samples on parallel machines, Parallel Computing, v.30 n.3, p.317-335, March 2004
	Chris Stolte , Robert Bosch , Pat Hanrahan , Mendel Rosenblum, Visualizing Application Behavior on Superscalar Processors, Proceedings of the 1999 IEEE Symposium on Information Visualization, p.10, October 24-29, 1999
	Humayun Khalid, Validating Trace-Driven Microarchitectural Simulations, IEEE Micro, v.20 n.6, p.76-82, November 2000
	Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Riccardo Locatelli , Giuseppe Maruccia , Francesco Papariello, OCCN: a NoC modeling framework for design exploration, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.2-3, p.129-163, February 2004
	Darell Suggs , Robert Reynolds, Constructing multiprocessor workload characterizations, Proceedings of the 33rd annual on Southeast regional conference, March 17-18, 1995, Clemson, South Carolina
	Lieven Eeckhout , Koen De Bosschere, Yet shorter warmup by combining no-state-loss and MRRL for sampled LRU cache simulation, Journal of Systems and Software, v.79 n.5, p.645-652, May 2006
	Pradip Bose, Testing for Function and Performance: Towards anIntegrated Processor Validation Methodology, Journal of Electronic Testing: Theory and Applications, v.16 n.1-2, p.29-48, Feb/April 2000
	Tariq Afzal, Performance modeling using the Motorola PowerPC timing simulator, ACM SIGARCH Computer Architecture News, v.23 n.4, p.9-18, Sept. 1995
	P. A. Sandon , Y.-C. Liao , T. E. Cook , D. M. Schultz , P. Martin-de-Nicolas, NStrace: a bus-driven instruction trace tool for PowerPC microprocessors, IBM Journal of Research and Development, v.41 n.3, p.331-344, May 1997