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Designing interconnection networks for multi-level packaging
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Source Conference on High Performance Networking and Computing archive
Proceedings of the 1993 ACM/IEEE conference on Supercomputing table of contents
Portland, Oregon, United States
Pages: 772 - 781  
Year of Publication: 1993
ISBN:0-8186-4340-4
Authors
M. T. Raghunath  Computer Science Division, University of California, Berkeley, CA
A. Ranade  Computer Science Division, University of California, Berkeley, CA
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Connection Machine Model CM-2 Technical Summary, 1987. Technical Report No: TR HA87- 4.
 
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W. J. Dally. Wire-Efficient VLSI Multiprocessor Communication Networks. In Advanced Research in VLSI, pages 391-415, 1987.
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Sivarama Dandamudi. Hierarchical Interconnection Networks for Multicomputer Systems. PhD thesis, University of Saskatchewan, Canada, 1988. Department of Computational Science 88- 18.
 
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P. Kermani and L. Kleinrock. Virtual Cut- Through: A New Computer Communication Switching Technique. Computer Networks, 3:267- 286, 1979.
 
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C. P. Kruskal and M. Snir. The performance of multistage interconnection networks for multiprocessors. IEEE Transactions on Computers, C-32(12):1091-1098, December 1983.
 
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Tom Leighton, Derek Lisinski, and Bruce Maggs. Empirical evaluation of randomly-wired multistage networks. In International Conference on Computer Design, 1990.
 
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Collaborative Colleagues:
M. T. Raghunath: colleagues
A. Ranade: colleagues